bf125e91f9
split spi stuff in three part: - v1 : basic spi peripheral - v1_frf : v1 spi with frf mode additional bit in spi_cr2 / spi_sr - v2 : spi with variable datasize, fifo and other fancy stuff. v1 maps to f1 chips v1_frf to f2, f4 and l0,l1 v2 to f0, f3 and l4 This breaks spi_master_init API for v2 devices : function prototype from common spi header used to be abused, with DFF bit reused for CRCL bit. New v2 spi_master_init does not handle anymore CRCL bits, as it does not usually mess with other crc configuration.
124 lines
3.8 KiB
C
124 lines
3.8 KiB
C
/** @addtogroup spi_defines
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H
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The order of header inclusion is important. spi.h includes the device
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specific memorymap.h header before including this header file.*/
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/** @cond */
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#ifdef LIBOPENCM3_SPI_H
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/** @endcond */
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#pragma once
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/**@{*/
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#include <libopencm3/stm32/common/spi_common_all.h>
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#define SPI_DR8(spi_base) MMIO8((spi_base) + 0x0c)
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#define SPI1_DR8 SPI_DR8(SPI1_BASE)
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#define SPI2_DR8 SPI_DR8(SPI2_BASE)
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#define SPI3_DR8 SPI_DR8(SPI3_BASE)
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/* CRCL: CRC Length */
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/****************************************************************************/
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/** @defgroup spi_crcl SPI crc length
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* @ingroup spi_defines
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*
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* @{*/
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#define SPI_CR1_CRCL_8BIT (0 << 11)
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#define SPI_CR1_CRCL_16BIT (1 << 11)
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/**@}*/
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#define SPI_CR1_CRCL (1 << 11)
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/* --- SPI_CR2 values ------------------------------------------------------ */
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/* LDMA_TX: Last DMA transfer for transmission */
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#define SPI_CR2_LDMA_TX (1 << 14)
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/* LDMA_RX: Last DMA transfer for reception */
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#define SPI_CR2_LDMA_RX (1 << 13)
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/* FRXTH: FIFO reception threshold */
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#define SPI_CR2_FRXTH (1 << 12)
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/* DS: Data size */
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/****************************************************************************/
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/** @defgroup spi_ds SPI data size
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* @ingroup spi_defines
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*
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* @{*/
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#define SPI_CR2_DS_4BIT (0x3 << 8)
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#define SPI_CR2_DS_5BIT (0x4 << 8)
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#define SPI_CR2_DS_6BIT (0x5 << 8)
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#define SPI_CR2_DS_7BIT (0x6 << 8)
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#define SPI_CR2_DS_8BIT (0x7 << 8)
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#define SPI_CR2_DS_9BIT (0x8 << 8)
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#define SPI_CR2_DS_10BIT (0x9 << 8)
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#define SPI_CR2_DS_11BIT (0xA << 8)
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#define SPI_CR2_DS_12BIT (0xB << 8)
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#define SPI_CR2_DS_13BIT (0xC << 8)
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#define SPI_CR2_DS_14BIT (0xD << 8)
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#define SPI_CR2_DS_15BIT (0xE << 8)
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#define SPI_CR2_DS_16BIT (0xF << 8)
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/**@}*/
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#define SPI_CR2_DS_MASK (0xF << 8)
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/* NSSP: NSS pulse management */
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#define SPI_CR2_NSSP (1 << 3)
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/* --- SPI_SR values ------------------------------------------------------- */
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/* FTLVL[1:0]: FIFO Transmission Level */
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#define SPI_SR_FTLVL_FIFO_EMPTY (0x0 << 11)
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#define SPI_SR_FTLVL_QUARTER_FIFO (0x1 << 11)
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#define SPI_SR_FTLVL_HALF_FIFO (0x2 << 11)
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#define SPI_SR_FTLVL_FIFO_FULL (0x3 << 11)
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/* FRLVL[1:0]: FIFO Reception Level */
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#define SPI_SR_FRLVL_FIFO_EMPTY (0x0 << 9)
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#define SPI_SR_FRLVL_QUARTER_FIFO (0x1 << 9)
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#define SPI_SR_FRLVL_HALF_FIFO (0x2 << 9)
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#define SPI_SR_FRLVL_FIFO_FULL (0x3 << 9)
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/* --- Function prototypes ------------------------------------------------- */
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BEGIN_DECLS
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int spi_init_master(uint32_t spi, uint32_t br, uint32_t cpol, uint32_t cpha,
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uint32_t lsbfirst);
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void spi_set_crcl_8bit(uint32_t spi);
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void spi_set_crcl_16bit(uint32_t spi);
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void spi_set_data_size(uint32_t spi, uint16_t data_s);
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void spi_fifo_reception_threshold_8bit(uint32_t spi);
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void spi_fifo_reception_threshold_16bit(uint32_t spi);
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void spi_i2s_mode_spi_mode(uint32_t spi);
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void spi_send8(uint32_t spi, uint8_t data);
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uint8_t spi_read8(uint32_t spi);
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END_DECLS
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/** @cond */
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#else
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#warning "spi_common_v2.h should not be included explicitly, only via spi.h"
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#endif
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/** @endcond */
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/**@}*/
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