c72f3d588a
All the macro arguments that are user supplied, or potentially, wrap properly in () as good practice. Probably missed one or two, and a lot of them are possibly unnecessary, but it's straightforward to just do it always. Fixes github issue #321
119 lines
3.5 KiB
C
119 lines
3.5 KiB
C
/** @defgroup ssi_defines Synchronous Serial Interface
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*
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* @brief <b>Defined Constants and Types for the LM4F Synchronous Serial Interface (SSI)</b>
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*
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* @ingroup LM4Fxx_defines
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*
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* @version 1.0.0
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*
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* @author @htmlonly © @endhtmlonly 2014
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* Tiago Costa <nippius+github@gmail.com>
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*
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* @date 11 June 2014
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2014 Tiago Costa <nippius+github@gmail.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LM4F_SSI_H
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#define LM4F_SSI_H
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/**@{*/
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/lm4f/memorymap.h>
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/* =============================================================================
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* Convenience macros
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* ---------------------------------------------------------------------------*/
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/** @defgroup ssi_base SSI register base addresses
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* @{*/
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#define SSI0 SSI0_BASE
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#define SSI1 SSI1_BASE
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#define SSI2 SSI2_BASE
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#define SSI3 SSI3_BASE
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/** @} */
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/* =============================================================================
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* SSI registers
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* ---------------------------------------------------------------------------*/
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/* SSI Control 0 */
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#define SSI_CR0(port) MMIO32((port) + 0x000)
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/* SSI Control 1 */
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#define SSI_CR1(port) MMIO32((port) + 0x004)
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/* SSI Data */
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#define SSI_DR(port) MMIO32((port) + 0x008)
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/* SSI Satus */
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#define SSI_SR(port) MMIO32((port) + 0x00C)
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/* SSI Clock Prescale */
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#define SSI_CPSR(port) MMIO32((port) + 0x010)
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/* SSI Interrupt Mask */
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#define SSI_IM(port) MMIO32((port) + 0x014)
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/* SSI Raw Interrupt Status */
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#define SSI_RIS(port) MMIO32((port) + 0x018)
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/* SSI Masked Interrupt Status */
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#define SSI_MIS(port) MMIO32((port) + 0x01C)
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/* SSI Interrupt Clear */
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#define SSI_ICR(port) MMIO32((port) + 0x020)
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/* SSI DMA Control */
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#define SSI_DMACTL(port) MMIO32((port) + 0x024)
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/* SSI Clock Configuration */
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#define SSI_CC(port) MMIO32((port) + 0xFC8)
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/* SSI Peripheral Identification */
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#define SSI_PERIPH_ID4(port) MMIO32((port) + 0xFD0)
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#define SSI_PERIPH_ID5(port) MMIO32((port) + 0xFD4)
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#define SSI_PERIPH_ID6(port) MMIO32((port) + 0xFD8)
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#define SSI_PERIPH_ID7(port) MMIO32((port) + 0xFDC)
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#define SSI_PERIPH_ID0(port) MMIO32((port) + 0xFE0)
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#define SSI_PERIPH_ID1(port) MMIO32((port) + 0xFE4)
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#define SSI_PERIPH_ID2(port) MMIO32((port) + 0xFE8)
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#define SSI_PERIPH_ID3(port) MMIO32((port) + 0xFEC)
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/* SSI PrimeCell Identification */
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#define SSI_PCELL_ID0(port) MMIO32((port) + 0xFF0)
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#define SSI_PCELL_ID1(port) MMIO32((port) + 0xFF4)
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#define SSI_PCELL_ID2(port) MMIO32((port) + 0xFF8)
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#define SSI_PCELL_ID3(port) MMIO32((port) + 0xFFC)
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/* =============================================================================
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* Function prototypes
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* ---------------------------------------------------------------------------*/
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BEGIN_DECLS
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END_DECLS
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/**@}*/
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#endif /* LM4F_SSI_H */
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