94 lines
3.9 KiB
C
94 lines
3.9 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2012 Silvio Gissi <silvio.gissi@outlook.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LPC17XX_MEMORYMAP_H
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#define LPC17XX_MEMORYMAP_H
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#include <libopencm3/cm3/memorymap.h>
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/* --- LPC17XX specific peripheral definitions ----------------------------- */
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/* Memory map for all busses */
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#define PERIPH_BASE_GPIO (0x2009C000U)
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#define PERIPH_BASE_APB0 (0x40000000U)
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#define PERIPH_BASE_APB1 (0x40080000U)
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#define PERIPH_BASE_AHB (0x50000000U)
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/* Register boundary addresses */
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/* GPIO */
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#define GPIO_PIO0_BASE (PERIPH_BASE_GPIO + 0x00)
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#define GPIO_PIO1_BASE (PERIPH_BASE_GPIO + 0x20)
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#define GPIO_PIO2_BASE (PERIPH_BASE_GPIO + 0x40)
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#define GPIO_PIO3_BASE (PERIPH_BASE_GPIO + 0x60)
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#define GPIO_PIO4_BASE (PERIPH_BASE_GPIO + 0x80)
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/* APB0 */
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#define WDT_BASE (PERIPH_BASE_APB0 + 0x00000)
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#define TIMER0_BASE (PERIPH_BASE_APB0 + 0x04000)
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#define TIMER1_BASE (PERIPH_BASE_APB0 + 0x08000)
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#define UART0_BASE (PERIPH_BASE_APB0 + 0x0c000)
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#define UART1_BASE (PERIPH_BASE_APB0 + 0x10000)
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/* PERIPH_BASE_APB0 + 0X14000 (0x4001 4000 - 0x4001 7FFF): Reserved */
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#define PWM1_BASE (PERIPH_BASE_APB0 + 0x18000)
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#define I2C0_BASE (PERIPH_BASE_APB0 + 0x1c000)
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#define SPI_BASE (PERIPH_BASE_APB0 + 0x20000)
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#define RTC_BASE (PERIPH_BASE_APB0 + 0x24000)
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#define GPIOINTERRUPT_BASE (PERIPH_BASE_APB0 + 0x28000)
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#define PINCONNECT_BASE (PERIPH_BASE_APB0 + 0x2c000)
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#define SSP1_BASE (PERIPH_BASE_APB0 + 0x30000)
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#define ADC_BASE (PERIPH_BASE_APB0 + 0x34000)
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#define CANAFRAM_BASE (PERIPH_BASE_APB0 + 0x38000)
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#define CANAFREG_BASE (PERIPH_BASE_APB0 + 0x3C000)
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#define CANCOMMONREG_BASE (PERIPH_BASE_APB0 + 0x40000)
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#define CAN1_BASE (PERIPH_BASE_APB0 + 0x44000)
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#define CAN2_BASE (PERIPH_BASE_APB0 + 0x48000)
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/* PERIPH_BASE_APB0 + 0X4C000 (0x4004 C000 - 0x4005 BFFF): Reserved */
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#define I2C1_BASE (PERIPH_BASE_APB0 + 0x5C000)
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/* PERIPH_BASE_APB0 + 0X60000 (0x4006 0000 - 0x4007 BFFF): Reserved */
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/* APB1 */
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/* PERIPH_BASE_APB1 + 0X00000 (0x4008 0000 - 0x4008 7FFF): Reserved */
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#define SSP0_BASE (PERIPH_BASE_APB1 + 0x08000)
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#define DAC_BASE (PERIPH_BASE_APB1 + 0x0c000)
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#define TIMER2_BASE (PERIPH_BASE_APB1 + 0x10000)
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#define TIMER3_BASE (PERIPH_BASE_APB1 + 0x14000)
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#define UART2_BASE (PERIPH_BASE_APB1 + 0x18000)
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#define UART3_BASE (PERIPH_BASE_APB1 + 0x1c000)
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#define I2C2_BASE (PERIPH_BASE_APB1 + 0x20000)
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/* PERIPH_BASE_APB1 + 0X24000 (0x400A 4000 - 0x400A 7FFF): Reserved */
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#define I2S_BASE (PERIPH_BASE_APB1 + 0x28000)
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/* PERIPH_BASE_APB1 + 0X2C000 (0x400A C000 - 0x400A FFFF): Reserved */
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#define RIT_BASE (PERIPH_BASE_APB1 + 0x30000)
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/* PERIPH_BASE_APB1 + 0X34000 (0x400B 4000 - 0x400B 7FFF): Reserved */
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#define MCPWM_BASE (PERIPH_BASE_APB1 + 0x38000)
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#define QEI_BASE (PERIPH_BASE_APB1 + 0x3c000)
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/* PERIPH_BASE_APB1 + 0X40000 (0x400C 0000 - 0x400F BFFF): Reserved */
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#define SYSCON_BASE (PERIPH_BASE_APB1 + 0x7c000)
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/* AHB */
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#define ETHERNET_BASE (PERIPH_BASE_AHB + 0x00000)
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#define GPDMA_BASE (PERIPH_BASE_AHB + 0x04000)
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/* PERIPH_BASE_AHB + 0X08000 (0x5000 8000 - 0x5000 BFFF): Reserved */
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#define USB_BASE (PERIPH_BASE_AHB + 0x0c000)
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/* PERIPH_BASE_AHB + 0X10000 (0x5001 0000 - 0x501F FFFF): Reserved */
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#endif
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