103 lines
3.1 KiB
C
103 lines
3.1 KiB
C
/** @defgroup pwr_defines Power Defines
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@brief <b>Defined Constants and Types for the LPC17xx Power Control</b>
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@ingroup LPC17xx_defines
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2013 Silvio Gissi <silvio.gissi@outlook.com>
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@date 17 August 2013
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Silvio Gissi <silvio.gissi@outlook.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LPC17XX_POWER_H
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#define LPC17XX_POWER_H
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#include <libopencm3/lpc17xx/memorymap.h>
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#include <libopencm3/cm3/common.h>
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/* --- Clock registers ----------------------------------------------------- */
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/* Power Control */
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#define PWR_PCON MMIO32(SYSCON_BASE + 0x0c0)
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#define PWR_PCONP MMIO32(SYSCON_BASE + 0x0c4)
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/* PWR_PCON Values */
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#define PWR_PCON_MODE_SLEEP 0x00
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#define PWR_PCON_MODE_POWER_DOWN 0x01
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/* PWR_PCON_MODE_RESERVED 0x02*/
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#define PWR_PCON_MODE_DEEPSLEEP 0x03
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#define PWR_PCON_BODRPM (1 << 2)
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#define PWR_PCON_BOGD (1 << 3)
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#define PWR_PCON_BORD (1 << 4)
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/* Reserved: [7:5] */
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#define PWR_PCON_SMFLAG (1 << 8)
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#define PWR_PCON_DSFLAG (1 << 9)
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#define PWR_PCON_PDFLAG (1 << 10)
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#define PWR_PCON_DPDFLAG (1 << 11)
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/* Reserved: [31:12] */
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/* PWR_PCONP Values */
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/* Reserved: [0] */
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#define PWR_PCONP_TIMER0 (1 << 1)
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#define PWR_PCONP_TIMER1 (1 << 2)
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#define PWR_PCONP_UART0 (1 << 3)
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#define PWR_PCONP_UART1 (1 << 4)
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/* Reserved: [5] */
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#define PWR_PCONP_PWM1 (1 << 6)
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#define PWR_PCONP_I2C0 (1 << 7)
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#define PWR_PCONP_SPI (1 << 8)
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#define PWR_PCONP_RTC (1 << 9)
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#define PWR_PCONP_SSP1 (1 << 10)
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/* Reserved: [11] */
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#define PWR_PCONP_ADC (1 << 12)
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#define PWR_PCONP_CAN1 (1 << 13)
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#define PWR_PCONP_CAN2 (1 << 14)
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#define PWR_PCONP_GPIO (1 << 15)
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#define PWR_PCONP_RIT (1 << 16)
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#define PWR_PCONP_MCPWM (1 << 17)
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#define PWR_PCONP_QEI (1 << 18)
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#define PWR_PCONP_I2C1 (1 << 19)
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/* Reserved: [20] */
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#define PWR_PCONP_SSP0 (1 << 21)
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#define PWR_PCONP_TIMER2 (1 << 22)
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#define PWR_PCONP_TIMER3 (1 << 23)
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#define PWR_PCONP_UART2 (1 << 24)
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#define PWR_PCONP_UART3 (1 << 25)
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#define PWR_PCONP_I2C2 (1 << 26)
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#define PWR_PCONP_I2S (1 << 27)
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/* Reserved: [28] */
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#define PWR_PCONP_GPDMA (1 << 29)
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#define PWR_PCONP_ETHERNET (1 << 30)
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#define PWR_PCONP_USB (1 << 31)
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BEGIN_DECLS
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void pwr_enable_peripherals(uint32_t peripherals);
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void pwr_disable_peripherals(uint32_t peripherals);
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/* TODO Sleep, Deep Sleep, Power Down and Deep Power Down modes */
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END_DECLS
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#endif
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