403 lines
14 KiB
C
403 lines
14 KiB
C
/** @defgroup ccu_defines Clock Control Unit Defines
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@brief <b>Defined Constants and Types for the LPC43xx Clock Control Unit</b>
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@ingroup LPC43xx_defines
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com>
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@date 10 March 2013
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LPC43XX_CCU_H
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#define LPC43XX_CCU_H
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/**@{*/
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/lpc43xx/memorymap.h>
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/* --- CCU1 registers ------------------------------------------------------ */
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/* CCU1 power mode register */
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#define CCU1_PM MMIO32(CCU1_BASE + 0x000)
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/* CCU1 base clock status register */
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#define CCU1_BASE_STAT MMIO32(CCU1_BASE + 0x004)
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/* CLK_APB3_BUS clock configuration register */
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#define CCU1_CLK_APB3_BUS_CFG MMIO32(CCU1_BASE + 0x100)
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/* CLK_APB3_BUS clock status register */
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#define CCU1_CLK_APB3_BUS_STAT MMIO32(CCU1_BASE + 0x104)
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/* CLK_APB3_I2C1 configuration register */
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#define CCU1_CLK_APB3_I2C1_CFG MMIO32(CCU1_BASE + 0x108)
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/* CLK_APB3_I2C1 status register */
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#define CCU1_CLK_APB3_I2C1_STAT MMIO32(CCU1_BASE + 0x10C)
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/* CLK_APB3_DAC configuration register */
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#define CCU1_CLK_APB3_DAC_CFG MMIO32(CCU1_BASE + 0x110)
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/* CLK_APB3_DAC status register */
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#define CCU1_CLK_APB3_DAC_STAT MMIO32(CCU1_BASE + 0x114)
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/* CLK_APB3_ADC0 configuration register */
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#define CCU1_CLK_APB3_ADC0_CFG MMIO32(CCU1_BASE + 0x118)
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/* CLK_APB3_ADC0 status register */
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#define CCU1_CLK_APB3_ADC0_STAT MMIO32(CCU1_BASE + 0x11C)
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/* CLK_APB3_ADC1 configuration register */
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#define CCU1_CLK_APB3_ADC1_CFG MMIO32(CCU1_BASE + 0x120)
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/* CLK_APB3_ADC1 status register */
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#define CCU1_CLK_APB3_ADC1_STAT MMIO32(CCU1_BASE + 0x124)
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/* CLK_APB3_CAN0 configuration register */
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#define CCU1_CLK_APB3_CAN0_CFG MMIO32(CCU1_BASE + 0x128)
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/* CLK_APB3_CAN0 status register */
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#define CCU1_CLK_APB3_CAN0_STAT MMIO32(CCU1_BASE + 0x12C)
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/* CLK_APB1_BUS configuration register */
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#define CCU1_CLK_APB1_BUS_CFG MMIO32(CCU1_BASE + 0x200)
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/* CLK_APB1_BUS status register */
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#define CCU1_CLK_APB1_BUS_STAT MMIO32(CCU1_BASE + 0x204)
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/* CLK_APB1_MOTOCON configuration register */
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#define CCU1_CLK_APB1_MOTOCONPWM_CFG MMIO32(CCU1_BASE + 0x208)
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/* CLK_APB1_MOTOCON status register */
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#define CCU1_CLK_APB1_MOTOCONPWM_STAT MMIO32(CCU1_BASE + 0x20C)
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/* CLK_APB1_I2C0 configuration register */
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#define CCU1_CLK_APB1_I2C0_CFG MMIO32(CCU1_BASE + 0x210)
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/* CLK_APB1_I2C0 status register */
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#define CCU1_CLK_APB1_I2C0_STAT MMIO32(CCU1_BASE + 0x214)
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/* CLK_APB1_I2S configuration register */
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#define CCU1_CLK_APB1_I2S_CFG MMIO32(CCU1_BASE + 0x218)
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/* CLK_APB1_I2S status register */
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#define CCU1_CLK_APB1_I2S_STAT MMIO32(CCU1_BASE + 0x21C)
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/* CLK_APB3_CAN1 configuration register */
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#define CCU1_CLK_APB1_CAN1_CFG MMIO32(CCU1_BASE + 0x220)
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/* CLK_APB3_CAN1 status register */
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#define CCU1_CLK_APB1_CAN1_STAT MMIO32(CCU1_BASE + 0x224)
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/* CLK_SPIFI configuration register */
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#define CCU1_CLK_SPIFI_CFG MMIO32(CCU1_BASE + 0x300)
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/* CLK_SPIFI status register */
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#define CCU1_CLK_SPIFI_STAT MMIO32(CCU1_BASE + 0x304)
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/* CLK_M4_BUS configuration register */
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#define CCU1_CLK_M4_BUS_CFG MMIO32(CCU1_BASE + 0x400)
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/* CLK_M4_BUS status register */
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#define CCU1_CLK_M4_BUS_STAT MMIO32(CCU1_BASE + 0x404)
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/* CLK_M4_SPIFI configuration register */
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#define CCU1_CLK_M4_SPIFI_CFG MMIO32(CCU1_BASE + 0x408)
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/* CLK_M4_SPIFI status register */
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#define CCU1_CLK_M4_SPIFI_STAT MMIO32(CCU1_BASE + 0x40C)
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/* CLK_M4_GPIO configuration register */
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#define CCU1_CLK_M4_GPIO_CFG MMIO32(CCU1_BASE + 0x410)
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/* CLK_M4_GPIO status register */
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#define CCU1_CLK_M4_GPIO_STAT MMIO32(CCU1_BASE + 0x414)
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/* CLK_M4_LCD configuration register */
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#define CCU1_CLK_M4_LCD_CFG MMIO32(CCU1_BASE + 0x418)
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/* CLK_M4_LCD status register */
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#define CCU1_CLK_M4_LCD_STAT MMIO32(CCU1_BASE + 0x41C)
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/* CLK_M4_ETHERNET configuration register */
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#define CCU1_CLK_M4_ETHERNET_CFG MMIO32(CCU1_BASE + 0x420)
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/* CLK_M4_ETHERNET status register */
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#define CCU1_CLK_M4_ETHERNET_STAT MMIO32(CCU1_BASE + 0x424)
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/* CLK_M4_USB0 configuration register */
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#define CCU1_CLK_M4_USB0_CFG MMIO32(CCU1_BASE + 0x428)
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/* CLK_M4_USB0 status register */
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#define CCU1_CLK_M4_USB0_STAT MMIO32(CCU1_BASE + 0x42C)
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/* CLK_M4_EMC configuration register */
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#define CCU1_CLK_M4_EMC_CFG MMIO32(CCU1_BASE + 0x430)
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/* CLK_M4_EMC status register */
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#define CCU1_CLK_M4_EMC_STAT MMIO32(CCU1_BASE + 0x434)
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/* CLK_M4_SDIO configuration register */
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#define CCU1_CLK_M4_SDIO_CFG MMIO32(CCU1_BASE + 0x438)
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/* CLK_M4_SDIO status register */
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#define CCU1_CLK_M4_SDIO_STAT MMIO32(CCU1_BASE + 0x43C)
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/* CLK_M4_DMA configuration register */
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#define CCU1_CLK_M4_DMA_CFG MMIO32(CCU1_BASE + 0x440)
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/* CLK_M4_DMA status register */
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#define CCU1_CLK_M4_DMA_STAT MMIO32(CCU1_BASE + 0x444)
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/* CLK_M4_M4CORE configuration register */
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#define CCU1_CLK_M4_M4CORE_CFG MMIO32(CCU1_BASE + 0x448)
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/* CLK_M4_M4CORE status register */
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#define CCU1_CLK_M4_M4CORE_STAT MMIO32(CCU1_BASE + 0x44C)
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/* CLK_M4_SCT configuration register */
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#define CCU1_CLK_M4_SCT_CFG MMIO32(CCU1_BASE + 0x468)
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/* CLK_M4_SCT status register */
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#define CCU1_CLK_M4_SCT_STAT MMIO32(CCU1_BASE + 0x46C)
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/* CLK_M4_USB1 configuration register */
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#define CCU1_CLK_M4_USB1_CFG MMIO32(CCU1_BASE + 0x470)
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/* CLK_M4_USB1 status register */
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#define CCU1_CLK_M4_USB1_STAT MMIO32(CCU1_BASE + 0x474)
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/* CLK_M4_EMCDIV configuration register */
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#define CCU1_CLK_M4_EMCDIV_CFG MMIO32(CCU1_BASE + 0x478)
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/* CLK_M4_EMCDIV status register */
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#define CCU1_CLK_M4_EMCDIV_STAT MMIO32(CCU1_BASE + 0x47C)
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/* CLK_M4_M0_CFG configuration register */
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#define CCU1_CLK_M4_M0APP_CFG MMIO32(CCU1_BASE + 0x490)
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/* CLK_M4_M0_STAT status register */
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#define CCU1_CLK_M4_M0APP_STAT MMIO32(CCU1_BASE + 0x494)
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/* CLK_M4_VADC_CFG configuration register */
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#define CCU1_CLK_M4_VADC_CFG MMIO32(CCU1_BASE + 0x498)
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/* CLK_M4_VADC_STAT configuration register */
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#define CCU1_CLK_M4_VADC_STAT MMIO32(CCU1_BASE + 0x49C)
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/* CLK_M4_WWDT configuration register */
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#define CCU1_CLK_M4_WWDT_CFG MMIO32(CCU1_BASE + 0x500)
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/* CLK_M4_WWDT status register */
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#define CCU1_CLK_M4_WWDT_STAT MMIO32(CCU1_BASE + 0x504)
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/* CLK_M4_UART0 configuration register */
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#define CCU1_CLK_M4_USART0_CFG MMIO32(CCU1_BASE + 0x508)
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/* CLK_M4_UART0 status register */
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#define CCU1_CLK_M4_USART0_STAT MMIO32(CCU1_BASE + 0x50C)
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/* CLK_M4_UART1 configuration register */
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#define CCU1_CLK_M4_UART1_CFG MMIO32(CCU1_BASE + 0x510)
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/* CLK_M4_UART1 status register */
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#define CCU1_CLK_M4_UART1_STAT MMIO32(CCU1_BASE + 0x514)
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/* CLK_M4_SSP0 configuration register */
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#define CCU1_CLK_M4_SSP0_CFG MMIO32(CCU1_BASE + 0x518)
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/* CLK_M4_SSP0 status register */
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#define CCU1_CLK_M4_SSP0_STAT MMIO32(CCU1_BASE + 0x51C)
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/* CLK_M4_TIMER0 configuration register */
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#define CCU1_CLK_M4_TIMER0_CFG MMIO32(CCU1_BASE + 0x520)
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/* CLK_M4_TIMER0 status register */
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#define CCU1_CLK_M4_TIMER0_STAT MMIO32(CCU1_BASE + 0x524)
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/* CLK_M4_TIMER1 configuration register */
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#define CCU1_CLK_M4_TIMER1_CFG MMIO32(CCU1_BASE + 0x528)
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/* CLK_M4_TIMER1 status register */
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#define CCU1_CLK_M4_TIMER1_STAT MMIO32(CCU1_BASE + 0x52C)
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/* CLK_M4_SCU configuration register */
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#define CCU1_CLK_M4_SCU_CFG MMIO32(CCU1_BASE + 0x530)
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/* CLK_M4_SCU status register */
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#define CCU1_CLK_M4_SCU_STAT MMIO32(CCU1_BASE + 0x534)
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/* CLK_M4_CREG configuration register */
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#define CCU1_CLK_M4_CREG_CFG MMIO32(CCU1_BASE + 0x538)
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/* CLK_M4_CREG status register */
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#define CCU1_CLK_M4_CREG_STAT MMIO32(CCU1_BASE + 0x53C)
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/* CLK_M4_RITIMER configuration register */
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#define CCU1_CLK_M4_RITIMER_CFG MMIO32(CCU1_BASE + 0x600)
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/* CLK_M4_RITIMER status register */
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#define CCU1_CLK_M4_RITIMER_STAT MMIO32(CCU1_BASE + 0x604)
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/* CLK_M4_UART2 configuration register */
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#define CCU1_CLK_M4_USART2_CFG MMIO32(CCU1_BASE + 0x608)
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/* CLK_M4_UART2 status register */
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#define CCU1_CLK_M4_USART2_STAT MMIO32(CCU1_BASE + 0x60C)
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/* CLK_M4_UART3 configuration register */
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#define CCU1_CLK_M4_USART3_CFG MMIO32(CCU1_BASE + 0x610)
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/* CLK_M4_UART3 status register */
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#define CCU1_CLK_M4_USART3_STAT MMIO32(CCU1_BASE + 0x614)
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/* CLK_M4_TIMER2 configuration register */
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#define CCU1_CLK_M4_TIMER2_CFG MMIO32(CCU1_BASE + 0x618)
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/* CLK_M4_TIMER2 status register */
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#define CCU1_CLK_M4_TIMER2_STAT MMIO32(CCU1_BASE + 0x61C)
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/* CLK_M4_TIMER3 configuration register */
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#define CCU1_CLK_M4_TIMER3_CFG MMIO32(CCU1_BASE + 0x620)
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/* CLK_M4_TIMER3 status register */
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#define CCU1_CLK_M4_TIMER3_STAT MMIO32(CCU1_BASE + 0x624)
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/* CLK_M4_SSP1 configuration register */
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#define CCU1_CLK_M4_SSP1_CFG MMIO32(CCU1_BASE + 0x628)
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/* CLK_M4_SSP1 status register */
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#define CCU1_CLK_M4_SSP1_STAT MMIO32(CCU1_BASE + 0x62C)
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/* CLK_M4_QEI configuration register */
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#define CCU1_CLK_M4_QEI_CFG MMIO32(CCU1_BASE + 0x630)
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/* CLK_M4_QEI status register */
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#define CCU1_CLK_M4_QEI_STAT MMIO32(CCU1_BASE + 0x634)
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/* CLK_PERIPH_BUS configuration register */
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#define CCU1_CLK_PERIPH_BUS_CFG MMIO32(CCU1_BASE + 0x700)
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/* CLK_PERIPH_BUS status register */
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#define CCU1_CLK_PERIPH_BUS_STAT MMIO32(CCU1_BASE + 0x704)
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/* CLK_PERIPH_CORE configuration register */
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#define CCU1_CLK_PERIPH_CORE_CFG MMIO32(CCU1_BASE + 0x710)
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/* CLK_PERIPH_CORE status register */
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#define CCU1_CLK_PERIPH_CORE_STAT MMIO32(CCU1_BASE + 0x714)
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/* CLK_PERIPH_SGPIO configuration register */
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#define CCU1_CLK_PERIPH_SGPIO_CFG MMIO32(CCU1_BASE + 0x718)
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/* CLK_PERIPH_SGPIO status register */
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#define CCU1_CLK_PERIPH_SGPIO_STAT MMIO32(CCU1_BASE + 0x71C)
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/* CLK_USB0 configuration register */
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#define CCU1_CLK_USB0_CFG MMIO32(CCU1_BASE + 0x800)
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/* CLK_USB0 status register */
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#define CCU1_CLK_USB0_STAT MMIO32(CCU1_BASE + 0x804)
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/* CLK_USB1 configuration register */
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#define CCU1_CLK_USB1_CFG MMIO32(CCU1_BASE + 0x900)
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/* CLK_USB1 status register */
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#define CCU1_CLK_USB1_STAT MMIO32(CCU1_BASE + 0x904)
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/* CLK_SPI configuration register */
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#define CCU1_CLK_SPI_CFG MMIO32(CCU1_BASE + 0xA00)
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/* CLK_SPI status register */
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#define CCU1_CLK_SPI_STAT MMIO32(CCU1_BASE + 0xA04)
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/* CLK_VADC configuration register */
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#define CCU1_CLK_VADC_CFG MMIO32(CCU1_BASE + 0xB00)
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/* CLK_VADC status register */
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#define CCU1_CLK_VADC_STAT MMIO32(CCU1_BASE + 0xB04)
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/* --- CCU2 registers ------------------------------------------------------ */
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/* CCU2 power mode register */
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#define CCU2_PM MMIO32(CCU2_BASE + 0x000)
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/* CCU2 base clocks status register */
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#define CCU2_BASE_STAT MMIO32(CCU2_BASE + 0x004)
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/* CLK_APLL configuration register */
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#define CCU2_CLK_APLL_CFG MMIO32(CCU2_BASE + 0x100)
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/* CLK_APLL status register */
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#define CCU2_CLK_APLL_STAT MMIO32(CCU2_BASE + 0x104)
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/* CLK_APB2_UART3 configuration register */
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#define CCU2_CLK_APB2_USART3_CFG MMIO32(CCU2_BASE + 0x200)
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/* CLK_APB2_UART3 status register */
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#define CCU2_CLK_APB2_USART3_STAT MMIO32(CCU2_BASE + 0x204)
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/* CLK_APB2_UART2 configuration register */
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#define CCU2_CLK_APB2_USART2_CFG MMIO32(CCU2_BASE + 0x300)
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/* CLK_APB2_UART2 status register */
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#define CCU2_CLK_APB2_USART2_STAT MMIO32(CCU2_BASE + 0x304)
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/* CLK_APB0_UART1 configuration register */
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#define CCU2_CLK_APB0_UART1_CFG MMIO32(CCU2_BASE + 0x400)
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/* CLK_APB0_UART1 status register */
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#define CCU2_CLK_APB0_UART1_STAT MMIO32(CCU2_BASE + 0x404)
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/* CLK_APB0_UART0 configuration register */
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#define CCU2_CLK_APB0_USART0_CFG MMIO32(CCU2_BASE + 0x500)
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/* CLK_APB0_UART0 status register */
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#define CCU2_CLK_APB0_USART0_STAT MMIO32(CCU2_BASE + 0x504)
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/* CLK_APB2_SSP1 configuration register */
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#define CCU2_CLK_APB2_SSP1_CFG MMIO32(CCU2_BASE + 0x600)
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/* CLK_APB2_SSP1 status register */
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#define CCU2_CLK_APB2_SSP1_STAT MMIO32(CCU2_BASE + 0x604)
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/* CLK_APB0_SSP0 configuration register */
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#define CCU2_CLK_APB0_SSP0_CFG MMIO32(CCU2_BASE + 0x700)
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/* CLK_APB0_SSP0 status register */
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#define CCU2_CLK_APB0_SSP0_STAT MMIO32(CCU2_BASE + 0x704)
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/* CLK_SDIO configuration register (for SD/MMC) */
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#define CCU2_CLK_SDIO_CFG MMIO32(CCU2_BASE + 0x800)
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/* CLK_SDIO status register (for SD/MMC) */
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#define CCU2_CLK_SDIO_STAT MMIO32(CCU2_BASE + 0x804)
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/**@}*/
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#endif
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