965 lines
36 KiB
C
965 lines
36 KiB
C
/** @defgroup cgu_defines Clock Generation Unit Defines
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*
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* @brief <b>Defined Constants and Types for the LPC43xx Clock Generation
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* Unit</b>
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*
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* @ingroup LPC43xx_defines
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*
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* @version 1.0.0
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*
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* @author @htmlonly © @endhtmlonly 2012 Michael Ossmann
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* <mike@ossmann.com>
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*
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* @date 10 March 2013
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LPC43XX_CGU_H
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#define CGU_LPC43XX_CGU_H
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/**@{*/
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/lpc43xx/memorymap.h>
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/* --- CGU registers ------------------------------------------------------- */
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/* Frequency monitor register */
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#define CGU_FREQ_MON MMIO32(CGU_BASE + 0x014)
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/* Crystal oscillator control register */
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#define CGU_XTAL_OSC_CTRL MMIO32(CGU_BASE + 0x018)
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/* PLL0USB status register */
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#define CGU_PLL0USB_STAT MMIO32(CGU_BASE + 0x01C)
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/* PLL0USB control register */
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#define CGU_PLL0USB_CTRL MMIO32(CGU_BASE + 0x020)
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/* PLL0USB M-divider register */
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#define CGU_PLL0USB_MDIV MMIO32(CGU_BASE + 0x024)
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/* PLL0USB N/P-divider register */
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#define CGU_PLL0USB_NP_DIV MMIO32(CGU_BASE + 0x028)
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/* PLL0AUDIO status register */
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#define CGU_PLL0AUDIO_STAT MMIO32(CGU_BASE + 0x02C)
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/* PLL0AUDIO control register */
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#define CGU_PLL0AUDIO_CTRL MMIO32(CGU_BASE + 0x030)
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/* PLL0AUDIO M-divider register */
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#define CGU_PLL0AUDIO_MDIV MMIO32(CGU_BASE + 0x034)
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/* PLL0AUDIO N/P-divider register */
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#define CGU_PLL0AUDIO_NP_DIV MMIO32(CGU_BASE + 0x038)
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/* PLL0AUDIO fractional divider register */
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#define CGU_PLLAUDIO_FRAC MMIO32(CGU_BASE + 0x03C)
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/* PLL1 status register */
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#define CGU_PLL1_STAT MMIO32(CGU_BASE + 0x040)
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/* PLL1 control register */
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#define CGU_PLL1_CTRL MMIO32(CGU_BASE + 0x044)
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/* Integer divider A control register */
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#define CGU_IDIVA_CTRL MMIO32(CGU_BASE + 0x048)
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/* Integer divider B control register */
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#define CGU_IDIVB_CTRL MMIO32(CGU_BASE + 0x04C)
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/* Integer divider C control register */
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#define CGU_IDIVC_CTRL MMIO32(CGU_BASE + 0x050)
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/* Integer divider D control register */
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#define CGU_IDIVD_CTRL MMIO32(CGU_BASE + 0x054)
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/* Integer divider E control register */
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#define CGU_IDIVE_CTRL MMIO32(CGU_BASE + 0x058)
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/* Output stage 0 control register */
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#define CGU_BASE_SAFE_CLK MMIO32(CGU_BASE + 0x05C)
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/* Output stage 1 control register for base clock */
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#define CGU_BASE_USB0_CLK MMIO32(CGU_BASE + 0x060)
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/* Output stage 2 control register for base clock */
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#define CGU_BASE_PERIPH_CLK MMIO32(CGU_BASE + 0x064)
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/* Output stage 3 control register for base clock */
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#define CGU_BASE_USB1_CLK MMIO32(CGU_BASE + 0x068)
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/* Output stage 4 control register for base clock */
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#define CGU_BASE_M4_CLK MMIO32(CGU_BASE + 0x06C)
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/* Output stage 5 control register for base clock */
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#define CGU_BASE_SPIFI_CLK MMIO32(CGU_BASE + 0x070)
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/* Output stage 6 control register for base clock */
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#define CGU_BASE_SPI_CLK MMIO32(CGU_BASE + 0x074)
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/* Output stage 7 control register for base clock */
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#define CGU_BASE_PHY_RX_CLK MMIO32(CGU_BASE + 0x078)
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/* Output stage 8 control register for base clock */
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#define CGU_BASE_PHY_TX_CLK MMIO32(CGU_BASE + 0x07C)
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/* Output stage 9 control register for base clock */
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#define CGU_BASE_APB1_CLK MMIO32(CGU_BASE + 0x080)
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/* Output stage 10 control register for base clock */
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#define CGU_BASE_APB3_CLK MMIO32(CGU_BASE + 0x084)
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/* Output stage 11 control register for base clock */
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#define CGU_BASE_LCD_CLK MMIO32(CGU_BASE + 0x088)
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/* Output stage 12 control register for base clock */
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#define CGU_BASE_VADC_CLK MMIO32(CGU_BASE + 0x08C)
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/* Output stage 13 control register for base clock */
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#define CGU_BASE_SDIO_CLK MMIO32(CGU_BASE + 0x090)
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/* Output stage 14 control register for base clock */
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#define CGU_BASE_SSP0_CLK MMIO32(CGU_BASE + 0x094)
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/* Output stage 15 control register for base clock */
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#define CGU_BASE_SSP1_CLK MMIO32(CGU_BASE + 0x098)
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/* Output stage 16 control register for base clock */
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#define CGU_BASE_UART0_CLK MMIO32(CGU_BASE + 0x09C)
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/* Output stage 17 control register for base clock */
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#define CGU_BASE_UART1_CLK MMIO32(CGU_BASE + 0x0A0)
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/* Output stage 18 control register for base clock */
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#define CGU_BASE_UART2_CLK MMIO32(CGU_BASE + 0x0A4)
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/* Output stage 19 control register for base clock */
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#define CGU_BASE_UART3_CLK MMIO32(CGU_BASE + 0x0A8)
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/* Output stage 20 control register for base clock */
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#define CGU_BASE_OUT_CLK MMIO32(CGU_BASE + 0x0AC)
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/* Reserved output stage */
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#define CGU_OUTCLK_21_CTRL MMIO32(CGU_BASE + 0x0B0)
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/* Reserved output stage */
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#define CGU_OUTCLK_22_CTRL MMIO32(CGU_BASE + 0x0B4)
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/* Reserved output stage */
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#define CGU_OUTCLK_23_CTRL MMIO32(CGU_BASE + 0x0B8)
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/* Reserved output stage */
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#define CGU_OUTCLK_24_CTRL MMIO32(CGU_BASE + 0x0BC)
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/* Output stage 25 control register for base clock */
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#define CGU_BASE_APLL_CLK MMIO32(CGU_BASE + 0x0C0)
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/* Output stage 26 control CLK register for base clock */
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#define CGU_BASE_CGU_OUT0_CLK MMIO32(CGU_BASE + 0x0C4)
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/* Output stage 27 control CLK register for base clock */
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#define CGU_BASE_CGU_OUT1_CLK MMIO32(CGU_BASE + 0x0C8)
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/* --- CGU_FREQ_MON values -------------------------------------- */
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/* RCNT: 9-bit reference clock-counter value */
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#define CGU_FREQ_MON_RCNT_SHIFT (0)
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#define CGU_FREQ_MON_RCNT_MASK (0x1ff << CGU_FREQ_MON_RCNT_SHIFT)
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#define CGU_FREQ_MON_RCNT(x) ((x) << CGU_FREQ_MON_RCNT_SHIFT)
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/* FCNT: 14-bit selected clock-counter value */
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#define CGU_FREQ_MON_FCNT_SHIFT (9)
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#define CGU_FREQ_MON_FCNT_MASK (0x3fff << CGU_FREQ_MON_FCNT_SHIFT)
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#define CGU_FREQ_MON_FCNT(x) ((x) << CGU_FREQ_MON_FCNT_SHIFT)
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/* MEAS: Measure frequency */
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#define CGU_FREQ_MON_MEAS_SHIFT (23)
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#define CGU_FREQ_MON_MEAS (1 << CGU_FREQ_MON_MEAS_SHIFT)
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/* CLK_SEL: Clock-source selection for the clock to be measured */
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#define CGU_FREQ_MON_CLK_SEL_SHIFT (24)
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#define CGU_FREQ_MON_CLK_SEL_MASK (0x1f << CGU_FREQ_MON_CLK_SEL_SHIFT)
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#define CGU_FREQ_MON_CLK_SEL(x) ((x) << CGU_FREQ_MON_CLK_SEL_SHIFT)
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/* --- CGU_XTAL_OSC_CTRL values --------------------------------- */
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/* ENABLE: Oscillator-pad enable */
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#define CGU_XTAL_OSC_CTRL_ENABLE_SHIFT (0)
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#define CGU_XTAL_OSC_CTRL_ENABLE (1 << CGU_XTAL_OSC_CTRL_ENABLE_SHIFT)
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/* BYPASS: Configure crystal operation or external-clock input pin XTAL1 */
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#define CGU_XTAL_OSC_CTRL_BYPASS_SHIFT (1)
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#define CGU_XTAL_OSC_CTRL_BYPASS (1 << CGU_XTAL_OSC_CTRL_BYPASS_SHIFT)
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/* HF: Select frequency range */
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#define CGU_XTAL_OSC_CTRL_HF_SHIFT (2)
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#define CGU_XTAL_OSC_CTRL_HF (1 << CGU_XTAL_OSC_CTRL_HF_SHIFT)
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/* --- CGU_PLL0USB_STAT values ---------------------------------- */
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/* LOCK: PLL0 lock indicator */
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#define CGU_PLL0USB_STAT_LOCK_SHIFT (0)
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#define CGU_PLL0USB_STAT_LOCK (1 << CGU_PLL0USB_STAT_LOCK_SHIFT)
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/* FR: PLL0 free running indicator */
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#define CGU_PLL0USB_STAT_FR_SHIFT (1)
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#define CGU_PLL0USB_STAT_FR (1 << CGU_PLL0USB_STAT_FR_SHIFT)
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/* --- CGU_PLL0USB_CTRL values ---------------------------------- */
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/* PD: PLL0 power down */
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#define CGU_PLL0USB_CTRL_PD_SHIFT (0)
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#define CGU_PLL0USB_CTRL_PD (1 << CGU_PLL0USB_CTRL_PD_SHIFT)
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/* BYPASS: Input clock bypass control */
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#define CGU_PLL0USB_CTRL_BYPASS_SHIFT (1)
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#define CGU_PLL0USB_CTRL_BYPASS (1 << CGU_PLL0USB_CTRL_BYPASS_SHIFT)
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/* DIRECTI: PLL0 direct input */
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#define CGU_PLL0USB_CTRL_DIRECTI_SHIFT (2)
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#define CGU_PLL0USB_CTRL_DIRECTI (1 << CGU_PLL0USB_CTRL_DIRECTI_SHIFT)
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/* DIRECTO: PLL0 direct output */
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#define CGU_PLL0USB_CTRL_DIRECTO_SHIFT (3)
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#define CGU_PLL0USB_CTRL_DIRECTO (1 << CGU_PLL0USB_CTRL_DIRECTO_SHIFT)
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/* CLKEN: PLL0 clock enable */
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#define CGU_PLL0USB_CTRL_CLKEN_SHIFT (4)
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#define CGU_PLL0USB_CTRL_CLKEN (1 << CGU_PLL0USB_CTRL_CLKEN_SHIFT)
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/* FRM: Free running mode */
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#define CGU_PLL0USB_CTRL_FRM_SHIFT (6)
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#define CGU_PLL0USB_CTRL_FRM (1 << CGU_PLL0USB_CTRL_FRM_SHIFT)
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/* AUTOBLOCK: Block clock automatically during frequency change */
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#define CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT (11)
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#define CGU_PLL0USB_CTRL_AUTOBLOCK (1 << CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT)
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/* CLK_SEL: Clock source selection */
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#define CGU_PLL0USB_CTRL_CLK_SEL_SHIFT (24)
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#define CGU_PLL0USB_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT)
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#define CGU_PLL0USB_CTRL_CLK_SEL(x) ((x) << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT)
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/* --- CGU_PLL0USB_MDIV values ---------------------------------- */
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/* MDEC: Decoded M-divider coefficient value */
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#define CGU_PLL0USB_MDIV_MDEC_SHIFT (0)
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#define CGU_PLL0USB_MDIV_MDEC_MASK (0x1ffff << CGU_PLL0USB_MDIV_MDEC_SHIFT)
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#define CGU_PLL0USB_MDIV_MDEC(x) ((x) << CGU_PLL0USB_MDIV_MDEC_SHIFT)
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/* SELP: Bandwidth select P value */
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#define CGU_PLL0USB_MDIV_SELP_SHIFT (17)
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#define CGU_PLL0USB_MDIV_SELP_MASK (0x1f << CGU_PLL0USB_MDIV_SELP_SHIFT)
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#define CGU_PLL0USB_MDIV_SELP(x) ((x) << CGU_PLL0USB_MDIV_SELP_SHIFT)
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/* SELI: Bandwidth select I value */
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#define CGU_PLL0USB_MDIV_SELI_SHIFT (22)
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#define CGU_PLL0USB_MDIV_SELI_MASK (0x3f << CGU_PLL0USB_MDIV_SELI_SHIFT)
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#define CGU_PLL0USB_MDIV_SELI(x) ((x) << CGU_PLL0USB_MDIV_SELI_SHIFT)
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/* SELR: Bandwidth select R value */
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#define CGU_PLL0USB_MDIV_SELR_SHIFT (28)
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#define CGU_PLL0USB_MDIV_SELR_MASK (0xf << CGU_PLL0USB_MDIV_SELR_SHIFT)
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#define CGU_PLL0USB_MDIV_SELR(x) ((x) << CGU_PLL0USB_MDIV_SELR_SHIFT)
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/* --- CGU_PLL0USB_NP_DIV values -------------------------------- */
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/* PDEC: Decoded P-divider coefficient value */
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#define CGU_PLL0USB_NP_DIV_PDEC_SHIFT (0)
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#define CGU_PLL0USB_NP_DIV_PDEC_MASK (0x7f << CGU_PLL0USB_NP_DIV_PDEC_SHIFT)
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#define CGU_PLL0USB_NP_DIV_PDEC(x) ((x) << CGU_PLL0USB_NP_DIV_PDEC_SHIFT)
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/* NDEC: Decoded N-divider coefficient value */
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#define CGU_PLL0USB_NP_DIV_NDEC_SHIFT (12)
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#define CGU_PLL0USB_NP_DIV_NDEC_MASK (0x3ff << CGU_PLL0USB_NP_DIV_NDEC_SHIFT)
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#define CGU_PLL0USB_NP_DIV_NDEC(x) ((x) << CGU_PLL0USB_NP_DIV_NDEC_SHIFT)
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/* --- CGU_PLL0AUDIO_STAT values -------------------------------- */
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/* LOCK: PLL0 lock indicator */
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#define CGU_PLL0AUDIO_STAT_LOCK_SHIFT (0)
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#define CGU_PLL0AUDIO_STAT_LOCK (1 << CGU_PLL0AUDIO_STAT_LOCK_SHIFT)
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/* FR: PLL0 free running indicator */
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#define CGU_PLL0AUDIO_STAT_FR_SHIFT (1)
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#define CGU_PLL0AUDIO_STAT_FR (1 << CGU_PLL0AUDIO_STAT_FR_SHIFT)
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/* --- CGU_PLL0AUDIO_CTRL values -------------------------------- */
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/* PD: PLL0 power down */
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#define CGU_PLL0AUDIO_CTRL_PD_SHIFT (0)
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#define CGU_PLL0AUDIO_CTRL_PD (1 << CGU_PLL0AUDIO_CTRL_PD_SHIFT)
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/* BYPASS: Input clock bypass control */
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#define CGU_PLL0AUDIO_CTRL_BYPASS_SHIFT (1)
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#define CGU_PLL0AUDIO_CTRL_BYPASS (1 << CGU_PLL0AUDIO_CTRL_BYPASS_SHIFT)
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/* DIRECTI: PLL0 direct input */
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#define CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT (2)
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#define CGU_PLL0AUDIO_CTRL_DIRECTI (1 << CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT)
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/* DIRECTO: PLL0 direct output */
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#define CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT (3)
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#define CGU_PLL0AUDIO_CTRL_DIRECTO (1 << CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT)
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/* CLKEN: PLL0 clock enable */
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#define CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT (4)
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#define CGU_PLL0AUDIO_CTRL_CLKEN (1 << CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT)
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/* FRM: Free running mode */
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#define CGU_PLL0AUDIO_CTRL_FRM_SHIFT (6)
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#define CGU_PLL0AUDIO_CTRL_FRM (1 << CGU_PLL0AUDIO_CTRL_FRM_SHIFT)
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/* AUTOBLOCK: Block clock automatically during frequency change */
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#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT (11)
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#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK \
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(1 << CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT)
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/* PLLFRACT_REQ: Fractional PLL word write request */
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#define CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT (12)
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#define CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ \
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(1 << CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT)
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/* SEL_EXT: Select fractional divider */
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#define CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT (13)
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#define CGU_PLL0AUDIO_CTRL_SEL_EXT (1 << CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT)
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/* MOD_PD: Sigma-Delta modulator power-down */
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#define CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT (14)
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#define CGU_PLL0AUDIO_CTRL_MOD_PD (1 << CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT)
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/* CLK_SEL: Clock source selection */
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#define CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT (24)
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#define CGU_PLL0AUDIO_CTRL_CLK_SEL_MASK \
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(0x1f << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT)
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#define CGU_PLL0AUDIO_CTRL_CLK_SEL(x) \
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((x) << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT)
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/* --- CGU_PLL0AUDIO_MDIV values -------------------------------- */
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/* MDEC: Decoded M-divider coefficient value */
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#define CGU_PLL0AUDIO_MDIV_MDEC_SHIFT (0)
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#define CGU_PLL0AUDIO_MDIV_MDEC_MASK \
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(0x1ffff << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT)
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#define CGU_PLL0AUDIO_MDIV_MDEC(x) \
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((x) << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT)
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/* --- CGU_PLL0AUDIO_NP_DIV values ------------------------------ */
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/* PDEC: Decoded P-divider coefficient value */
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#define CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT (0)
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#define CGU_PLL0AUDIO_NP_DIV_PDEC_MASK \
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(0x7f << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT)
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#define CGU_PLL0AUDIO_NP_DIV_PDEC(x) \
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((x) << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT)
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/* NDEC: Decoded N-divider coefficient value */
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#define CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT (12)
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#define CGU_PLL0AUDIO_NP_DIV_NDEC_MASK \
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(0x3ff << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT)
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#define CGU_PLL0AUDIO_NP_DIV_NDEC(x) \
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((x) << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT)
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/* --- CGU_PLLAUDIO_FRAC values --------------------------------- */
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/* PLLFRACT_CTRL: PLL fractional divider control word */
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#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT (0)
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#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_MASK \
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(0x3fffff << CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT)
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#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL(x) \
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((x) << CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT)
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/* --- CGU_PLL1_STAT values ------------------------------------- */
|
|
|
|
/* LOCK: PLL1 lock indicator */
|
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#define CGU_PLL1_STAT_LOCK_SHIFT (0)
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#define CGU_PLL1_STAT_LOCK (1 << CGU_PLL1_STAT_LOCK_SHIFT)
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/* --- CGU_PLL1_CTRL values ------------------------------------- */
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/* PD: PLL1 power down */
|
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#define CGU_PLL1_CTRL_PD_SHIFT (0)
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#define CGU_PLL1_CTRL_PD (1 << CGU_PLL1_CTRL_PD_SHIFT)
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/* BYPASS: Input clock bypass control */
|
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#define CGU_PLL1_CTRL_BYPASS_SHIFT (1)
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#define CGU_PLL1_CTRL_BYPASS (1 << CGU_PLL1_CTRL_BYPASS_SHIFT)
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/* FBSEL: PLL feedback select */
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#define CGU_PLL1_CTRL_FBSEL_SHIFT (6)
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#define CGU_PLL1_CTRL_FBSEL (1 << CGU_PLL1_CTRL_FBSEL_SHIFT)
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/* DIRECT: PLL direct CCO output */
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#define CGU_PLL1_CTRL_DIRECT_SHIFT (7)
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#define CGU_PLL1_CTRL_DIRECT (1 << CGU_PLL1_CTRL_DIRECT_SHIFT)
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/* PSEL: Post-divider division ratio P */
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#define CGU_PLL1_CTRL_PSEL_SHIFT (8)
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#define CGU_PLL1_CTRL_PSEL_MASK (0x3 << CGU_PLL1_CTRL_PSEL_SHIFT)
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#define CGU_PLL1_CTRL_PSEL(x) ((x) << CGU_PLL1_CTRL_PSEL_SHIFT)
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/* AUTOBLOCK: Block clock automatically during frequency change */
|
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#define CGU_PLL1_CTRL_AUTOBLOCK_SHIFT (11)
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#define CGU_PLL1_CTRL_AUTOBLOCK (1 << CGU_PLL1_CTRL_AUTOBLOCK_SHIFT)
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/* NSEL: Pre-divider division ratio N */
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#define CGU_PLL1_CTRL_NSEL_SHIFT (12)
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#define CGU_PLL1_CTRL_NSEL_MASK (0x3 << CGU_PLL1_CTRL_NSEL_SHIFT)
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#define CGU_PLL1_CTRL_NSEL(x) ((x) << CGU_PLL1_CTRL_NSEL_SHIFT)
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/* MSEL: Feedback-divider division ratio (M) */
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#define CGU_PLL1_CTRL_MSEL_SHIFT (16)
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#define CGU_PLL1_CTRL_MSEL_MASK (0xff << CGU_PLL1_CTRL_MSEL_SHIFT)
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#define CGU_PLL1_CTRL_MSEL(x) ((x) << CGU_PLL1_CTRL_MSEL_SHIFT)
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/* CLK_SEL: Clock-source selection */
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#define CGU_PLL1_CTRL_CLK_SEL_SHIFT (24)
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#define CGU_PLL1_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL1_CTRL_CLK_SEL_SHIFT)
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#define CGU_PLL1_CTRL_CLK_SEL(x) ((x) << CGU_PLL1_CTRL_CLK_SEL_SHIFT)
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/* --- CGU_IDIVA_CTRL values ------------------------------------ */
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|
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/* PD: Integer divider power down */
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#define CGU_IDIVA_CTRL_PD_SHIFT (0)
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#define CGU_IDIVA_CTRL_PD (1 << CGU_IDIVA_CTRL_PD_SHIFT)
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/* IDIV: Integer divider A divider value (1/(IDIV + 1)) */
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#define CGU_IDIVA_CTRL_IDIV_SHIFT (2)
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#define CGU_IDIVA_CTRL_IDIV_MASK (0x3 << CGU_IDIVA_CTRL_IDIV_SHIFT)
|
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#define CGU_IDIVA_CTRL_IDIV(x) ((x) << CGU_IDIVA_CTRL_IDIV_SHIFT)
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|
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/* AUTOBLOCK: Block clock automatically during frequency change */
|
|
#define CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT (11)
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#define CGU_IDIVA_CTRL_AUTOBLOCK (1 << CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT)
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|
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/* CLK_SEL: Clock source selection */
|
|
#define CGU_IDIVA_CTRL_CLK_SEL_SHIFT (24)
|
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#define CGU_IDIVA_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVA_CTRL_CLK_SEL_SHIFT)
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#define CGU_IDIVA_CTRL_CLK_SEL(x) ((x) << CGU_IDIVA_CTRL_CLK_SEL_SHIFT)
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/* --- CGU_IDIVB_CTRL values ------------------------------------ */
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|
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/* PD: Integer divider power down */
|
|
#define CGU_IDIVB_CTRL_PD_SHIFT (0)
|
|
#define CGU_IDIVB_CTRL_PD (1 << CGU_IDIVB_CTRL_PD_SHIFT)
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/* IDIV: Integer divider B divider value (1/(IDIV + 1)) */
|
|
#define CGU_IDIVB_CTRL_IDIV_SHIFT (2)
|
|
#define CGU_IDIVB_CTRL_IDIV_MASK (0xf << CGU_IDIVB_CTRL_IDIV_SHIFT)
|
|
#define CGU_IDIVB_CTRL_IDIV(x) ((x) << CGU_IDIVB_CTRL_IDIV_SHIFT)
|
|
|
|
/* AUTOBLOCK: Block clock automatically during frequency change */
|
|
#define CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT (11)
|
|
#define CGU_IDIVB_CTRL_AUTOBLOCK (1 << CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT)
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|
|
/* CLK_SEL: Clock source selection */
|
|
#define CGU_IDIVB_CTRL_CLK_SEL_SHIFT (24)
|
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#define CGU_IDIVB_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVB_CTRL_CLK_SEL_SHIFT)
|
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#define CGU_IDIVB_CTRL_CLK_SEL(x) ((x) << CGU_IDIVB_CTRL_CLK_SEL_SHIFT)
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/* --- CGU_IDIVC_CTRL values ------------------------------------ */
|
|
|
|
/* PD: Integer divider power down */
|
|
#define CGU_IDIVC_CTRL_PD_SHIFT (0)
|
|
#define CGU_IDIVC_CTRL_PD (1 << CGU_IDIVC_CTRL_PD_SHIFT)
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|
|
/* IDIV: Integer divider C divider value (1/(IDIV + 1)) */
|
|
#define CGU_IDIVC_CTRL_IDIV_SHIFT (2)
|
|
#define CGU_IDIVC_CTRL_IDIV_MASK (0xf << CGU_IDIVC_CTRL_IDIV_SHIFT)
|
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#define CGU_IDIVC_CTRL_IDIV(x) ((x) << CGU_IDIVC_CTRL_IDIV_SHIFT)
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|
|
/* AUTOBLOCK: Block clock automatically during frequency change */
|
|
#define CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT (11)
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|
#define CGU_IDIVC_CTRL_AUTOBLOCK (1 << CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT)
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|
|
/* CLK_SEL: Clock source selection */
|
|
#define CGU_IDIVC_CTRL_CLK_SEL_SHIFT (24)
|
|
#define CGU_IDIVC_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVC_CTRL_CLK_SEL_SHIFT)
|
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#define CGU_IDIVC_CTRL_CLK_SEL(x) ((x) << CGU_IDIVC_CTRL_CLK_SEL_SHIFT)
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|
|
/* --- CGU_IDIVD_CTRL values ------------------------------------ */
|
|
|
|
/* PD: Integer divider power down */
|
|
#define CGU_IDIVD_CTRL_PD_SHIFT (0)
|
|
#define CGU_IDIVD_CTRL_PD (1 << CGU_IDIVD_CTRL_PD_SHIFT)
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|
|
/* IDIV: Integer divider D divider value (1/(IDIV + 1)) */
|
|
#define CGU_IDIVD_CTRL_IDIV_SHIFT (2)
|
|
#define CGU_IDIVD_CTRL_IDIV_MASK (0xf << CGU_IDIVD_CTRL_IDIV_SHIFT)
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#define CGU_IDIVD_CTRL_IDIV(x) ((x) << CGU_IDIVD_CTRL_IDIV_SHIFT)
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|
|
/* AUTOBLOCK: Block clock automatically during frequency change */
|
|
#define CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT (11)
|
|
#define CGU_IDIVD_CTRL_AUTOBLOCK (1 << CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT)
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|
|
/* CLK_SEL: Clock source selection */
|
|
#define CGU_IDIVD_CTRL_CLK_SEL_SHIFT (24)
|
|
#define CGU_IDIVD_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVD_CTRL_CLK_SEL_SHIFT)
|
|
#define CGU_IDIVD_CTRL_CLK_SEL(x) ((x) << CGU_IDIVD_CTRL_CLK_SEL_SHIFT)
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|
|
/* --- CGU_IDIVE_CTRL values ------------------------------------ */
|
|
|
|
/* PD: Integer divider power down */
|
|
#define CGU_IDIVE_CTRL_PD_SHIFT (0)
|
|
#define CGU_IDIVE_CTRL_PD (1 << CGU_IDIVE_CTRL_PD_SHIFT)
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|
|
/* IDIV: Integer divider E divider value (1/(IDIV + 1)) */
|
|
#define CGU_IDIVE_CTRL_IDIV_SHIFT (2)
|
|
#define CGU_IDIVE_CTRL_IDIV_MASK (0xff << CGU_IDIVE_CTRL_IDIV_SHIFT)
|
|
#define CGU_IDIVE_CTRL_IDIV(x) ((x) << CGU_IDIVE_CTRL_IDIV_SHIFT)
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|
|
|
/* AUTOBLOCK: Block clock automatically during frequency change */
|
|
#define CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT (11)
|
|
#define CGU_IDIVE_CTRL_AUTOBLOCK (1 << CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT)
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|
|
|
/* CLK_SEL: Clock source selection */
|
|
#define CGU_IDIVE_CTRL_CLK_SEL_SHIFT (24)
|
|
#define CGU_IDIVE_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVE_CTRL_CLK_SEL_SHIFT)
|
|
#define CGU_IDIVE_CTRL_CLK_SEL(x) ((x) << CGU_IDIVE_CTRL_CLK_SEL_SHIFT)
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|
|
|
/* --- CGU_BASE_SAFE_CLK values --------------------------------- */
|
|
|
|
/* PD: Output stage power down */
|
|
#define CGU_BASE_SAFE_CLK_PD_SHIFT (0)
|
|
#define CGU_BASE_SAFE_CLK_PD (1 << CGU_BASE_SAFE_CLK_PD_SHIFT)
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|
|
|
/* AUTOBLOCK: Block clock automatically during frequency change */
|
|
#define CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT (11)
|
|
#define CGU_BASE_SAFE_CLK_AUTOBLOCK (1 << CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT)
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|
|
|
/* CLK_SEL: Clock source selection */
|
|
#define CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT (24)
|
|
#define CGU_BASE_SAFE_CLK_CLK_SEL_MASK \
|
|
(0x1f << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT)
|
|
#define CGU_BASE_SAFE_CLK_CLK_SEL(x) \
|
|
((x) << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT)
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|
|
|
/* --- CGU_BASE_USB0_CLK values --------------------------------- */
|
|
|
|
/* PD: Output stage power down */
|
|
#define CGU_BASE_USB0_CLK_PD_SHIFT (0)
|
|
#define CGU_BASE_USB0_CLK_PD (1 << CGU_BASE_USB0_CLK_PD_SHIFT)
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|
|
|
/* AUTOBLOCK: Block clock automatically during frequency change */
|
|
#define CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT (11)
|
|
#define CGU_BASE_USB0_CLK_AUTOBLOCK (1 << CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT)
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|
|
|
/* CLK_SEL: Clock source selection */
|
|
#define CGU_BASE_USB0_CLK_CLK_SEL_SHIFT (24)
|
|
#define CGU_BASE_USB0_CLK_CLK_SEL_MASK \
|
|
(0x1f << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT)
|
|
#define CGU_BASE_USB0_CLK_CLK_SEL(x) \
|
|
((x) << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT)
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|
|
|
/* --- CGU_BASE_PERIPH_CLK values ------------------------------- */
|
|
|
|
/* PD: Output stage power down */
|
|
#define CGU_BASE_PERIPH_CLK_PD_SHIFT (0)
|
|
#define CGU_BASE_PERIPH_CLK_PD (1 << CGU_BASE_PERIPH_CLK_PD_SHIFT)
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|
|
|
/* AUTOBLOCK: Block clock automatically during frequency change */
|
|
#define CGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT (11)
|
|
#define CGU_BASE_PERIPH_CLK_AUTOBLOCK \
|
|
(1 << CGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT)
|
|
|
|
/* CLK_SEL: Clock source selection */
|
|
#define CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT (24)
|
|
#define CGU_BASE_PERIPH_CLK_CLK_SEL_MASK \
|
|
(0x1f << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT)
|
|
#define CGU_BASE_PERIPH_CLK_CLK_SEL(x) \
|
|
((x) << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT)
|
|
|
|
/* --- CGU_BASE_USB1_CLK values --------------------------------- */
|
|
|
|
/* PD: Output stage power down */
|
|
#define CGU_BASE_USB1_CLK_PD_SHIFT (0)
|
|
#define CGU_BASE_USB1_CLK_PD (1 << CGU_BASE_USB1_CLK_PD_SHIFT)
|
|
|
|
/* AUTOBLOCK: Block clock automatically during frequency change */
|
|
#define CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT (11)
|
|
#define CGU_BASE_USB1_CLK_AUTOBLOCK (1 << CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT)
|
|
|
|
/* CLK_SEL: Clock source selection */
|
|
#define CGU_BASE_USB1_CLK_CLK_SEL_SHIFT (24)
|
|
#define CGU_BASE_USB1_CLK_CLK_SEL_MASK \
|
|
(0x1f << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT)
|
|
#define CGU_BASE_USB1_CLK_CLK_SEL(x) \
|
|
((x) << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT)
|
|
|
|
/* --- CGU_BASE_M4_CLK values ----------------------------------- */
|
|
|
|
/* PD: Output stage power down */
|
|
#define CGU_BASE_M4_CLK_PD_SHIFT (0)
|
|
#define CGU_BASE_M4_CLK_PD (1 << CGU_BASE_M4_CLK_PD_SHIFT)
|
|
|
|
/* AUTOBLOCK: Block clock automatically during frequency change */
|
|
#define CGU_BASE_M4_CLK_AUTOBLOCK_SHIFT (11)
|
|
#define CGU_BASE_M4_CLK_AUTOBLOCK (1 << CGU_BASE_M4_CLK_AUTOBLOCK_SHIFT)
|
|
|
|
/* CLK_SEL: Clock source selection */
|
|
#define CGU_BASE_M4_CLK_CLK_SEL_SHIFT (24)
|
|
#define CGU_BASE_M4_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_M4_CLK_CLK_SEL_SHIFT)
|
|
#define CGU_BASE_M4_CLK_CLK_SEL(x) ((x) << CGU_BASE_M4_CLK_CLK_SEL_SHIFT)
|
|
|
|
/* --- CGU_BASE_SPIFI_CLK values -------------------------------- */
|
|
|
|
/* PD: Output stage power down */
|
|
#define CGU_BASE_SPIFI_CLK_PD_SHIFT (0)
|
|
#define CGU_BASE_SPIFI_CLK_PD (1 << CGU_BASE_SPIFI_CLK_PD_SHIFT)
|
|
|
|
/* AUTOBLOCK: Block clock automatically during frequency change */
|
|
#define CGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT (11)
|
|
#define CGU_BASE_SPIFI_CLK_AUTOBLOCK \
|
|
(1 << CGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT)
|
|
|
|
/* CLK_SEL: Clock source selection */
|
|
#define CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT (24)
|
|
#define CGU_BASE_SPIFI_CLK_CLK_SEL_MASK \
|
|
(0x1f << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT)
|
|
#define CGU_BASE_SPIFI_CLK_CLK_SEL(x) \
|
|
((x) << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT)
|
|
|
|
/* --- CGU_BASE_SPI_CLK values ---------------------------------- */
|
|
|
|
/* PD: Output stage power down */
|
|
#define CGU_BASE_SPI_CLK_PD_SHIFT (0)
|
|
#define CGU_BASE_SPI_CLK_PD (1 << CGU_BASE_SPI_CLK_PD_SHIFT)
|
|
|
|
/* AUTOBLOCK: Block clock automatically during frequency change */
|
|
#define CGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT (11)
|
|
#define CGU_BASE_SPI_CLK_AUTOBLOCK (1 << CGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT)
|
|
|
|
/* CLK_SEL: Clock source selection */
|
|
#define CGU_BASE_SPI_CLK_CLK_SEL_SHIFT (24)
|
|
#define CGU_BASE_SPI_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT)
|
|
#define CGU_BASE_SPI_CLK_CLK_SEL(x) ((x) << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT)
|
|
|
|
/* --- CGU_BASE_PHY_RX_CLK values ------------------------------- */
|
|
|
|
/* PD: Output stage power down */
|
|
#define CGU_BASE_PHY_RX_CLK_PD_SHIFT (0)
|
|
#define CGU_BASE_PHY_RX_CLK_PD (1 << CGU_BASE_PHY_RX_CLK_PD_SHIFT)
|
|
|
|
/* AUTOBLOCK: Block clock automatically during frequency change */
|
|
#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT (11)
|
|
#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK \
|
|
(1 << CGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT)
|
|
|
|
/* CLK_SEL: Clock source selection */
|
|
#define CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT (24)
|
|
#define CGU_BASE_PHY_RX_CLK_CLK_SEL_MASK \
|
|
(0x1f << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT)
|
|
#define CGU_BASE_PHY_RX_CLK_CLK_SEL(x) \
|
|
((x) << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT)
|
|
|
|
/* --- CGU_BASE_PHY_TX_CLK values ------------------------------- */
|
|
|
|
/* PD: Output stage power down */
|
|
#define CGU_BASE_PHY_TX_CLK_PD_SHIFT (0)
|
|
#define CGU_BASE_PHY_TX_CLK_PD (1 << CGU_BASE_PHY_TX_CLK_PD_SHIFT)
|
|
|
|
/* AUTOBLOCK: Block clock automatically during frequency change */
|
|
#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT (11)
|
|
#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK \
|
|
(1 << CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT)
|
|
|
|
/* CLK_SEL: Clock source selection */
|
|
#define CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT (24)
|
|
#define CGU_BASE_PHY_TX_CLK_CLK_SEL_MASK \
|
|
(0x1f << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT)
|
|
#define CGU_BASE_PHY_TX_CLK_CLK_SEL(x) \
|
|
((x) << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT)
|
|
|
|
/* --- CGU_BASE_APB1_CLK values --------------------------------- */
|
|
|
|
/* PD: Output stage power down */
|
|
#define CGU_BASE_APB1_CLK_PD_SHIFT (0)
|
|
#define CGU_BASE_APB1_CLK_PD (1 << CGU_BASE_APB1_CLK_PD_SHIFT)
|
|
|
|
/* AUTOBLOCK: Block clock automatically during frequency change */
|
|
#define CGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT (11)
|
|
#define CGU_BASE_APB1_CLK_AUTOBLOCK (1 << CGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT)
|
|
|
|
/* CLK_SEL: Clock source selection */
|
|
#define CGU_BASE_APB1_CLK_CLK_SEL_SHIFT (24)
|
|
#define CGU_BASE_APB1_CLK_CLK_SEL_MASK \
|
|
(0x1f << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT)
|
|
#define CGU_BASE_APB1_CLK_CLK_SEL(x) ((x) << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT)
|
|
|
|
/* --- CGU_BASE_APB3_CLK values --------------------------------- */
|
|
|
|
/* PD: Output stage power down */
|
|
#define CGU_BASE_APB3_CLK_PD_SHIFT (0)
|
|
#define CGU_BASE_APB3_CLK_PD (1 << CGU_BASE_APB3_CLK_PD_SHIFT)
|
|
|
|
/* AUTOBLOCK: Block clock automatically during frequency change */
|
|
#define CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT (11)
|
|
#define CGU_BASE_APB3_CLK_AUTOBLOCK (1 << CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT)
|
|
|
|
/* CLK_SEL: Clock source selection */
|
|
#define CGU_BASE_APB3_CLK_CLK_SEL_SHIFT (24)
|
|
#define CGU_BASE_APB3_CLK_CLK_SEL_MASK \
|
|
(0x1f << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT)
|
|
#define CGU_BASE_APB3_CLK_CLK_SEL(x) ((x) << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT)
|
|
|
|
/* --- CGU_BASE_LCD_CLK values ---------------------------------- */
|
|
|
|
/* PD: Output stage power down */
|
|
#define CGU_BASE_LCD_CLK_PD_SHIFT (0)
|
|
#define CGU_BASE_LCD_CLK_PD (1 << CGU_BASE_LCD_CLK_PD_SHIFT)
|
|
|
|
/* AUTOBLOCK: Block clock automatically during frequency change */
|
|
#define CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT (11)
|
|
#define CGU_BASE_LCD_CLK_AUTOBLOCK (1 << CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT)
|
|
|
|
/* CLK_SEL: Clock source selection */
|
|
#define CGU_BASE_LCD_CLK_CLK_SEL_SHIFT (24)
|
|
#define CGU_BASE_LCD_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT)
|
|
#define CGU_BASE_LCD_CLK_CLK_SEL(x) ((x) << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT)
|
|
|
|
/* --- CGU_BASE_VADC_CLK values --------------------------------- */
|
|
|
|
/* PD: Output stage power down */
|
|
#define CGU_BASE_VADC_CLK_PD_SHIFT (0)
|
|
#define CGU_BASE_VADC_CLK_PD (1 << CGU_BASE_VADC_CLK_PD_SHIFT)
|
|
|
|
/* AUTOBLOCK: Block clock automatically during frequency change */
|
|
#define CGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT (11)
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#define CGU_BASE_VADC_CLK_AUTOBLOCK (1 << CGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT)
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/* CLK_SEL: Clock source selection */
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#define CGU_BASE_VADC_CLK_CLK_SEL_SHIFT (24)
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#define CGU_BASE_VADC_CLK_CLK_SEL_MASK \
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(0x1f << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT)
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#define CGU_BASE_VADC_CLK_CLK_SEL(x) ((x) << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT)
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/* --- CGU_BASE_SDIO_CLK values --------------------------------- */
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/* PD: Output stage power down */
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#define CGU_BASE_SDIO_CLK_PD_SHIFT (0)
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#define CGU_BASE_SDIO_CLK_PD (1 << CGU_BASE_SDIO_CLK_PD_SHIFT)
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/* AUTOBLOCK: Block clock automatically during frequency change */
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#define CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT (11)
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#define CGU_BASE_SDIO_CLK_AUTOBLOCK (1 << CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT)
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/* CLK_SEL: Clock source selection */
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#define CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT (24)
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#define CGU_BASE_SDIO_CLK_CLK_SEL_MASK \
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(0x1f << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT)
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#define CGU_BASE_SDIO_CLK_CLK_SEL(x) ((x) << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT)
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/* --- CGU_BASE_SSP0_CLK values --------------------------------- */
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/* PD: Output stage power down */
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#define CGU_BASE_SSP0_CLK_PD_SHIFT (0)
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#define CGU_BASE_SSP0_CLK_PD (1 << CGU_BASE_SSP0_CLK_PD_SHIFT)
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/* AUTOBLOCK: Block clock automatically during frequency change */
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#define CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT (11)
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#define CGU_BASE_SSP0_CLK_AUTOBLOCK (1 << CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT)
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/* CLK_SEL: Clock source selection */
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#define CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT (24)
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#define CGU_BASE_SSP0_CLK_CLK_SEL_MASK \
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(0x1f << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT)
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#define CGU_BASE_SSP0_CLK_CLK_SEL(x) ((x) << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT)
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/* --- CGU_BASE_SSP1_CLK values --------------------------------- */
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/* PD: Output stage power down */
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#define CGU_BASE_SSP1_CLK_PD_SHIFT (0)
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#define CGU_BASE_SSP1_CLK_PD (1 << CGU_BASE_SSP1_CLK_PD_SHIFT)
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/* AUTOBLOCK: Block clock automatically during frequency change */
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#define CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT (11)
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#define CGU_BASE_SSP1_CLK_AUTOBLOCK (1 << CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT)
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/* CLK_SEL: Clock source selection */
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#define CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT (24)
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#define CGU_BASE_SSP1_CLK_CLK_SEL_MASK \
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(0x1f << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT)
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#define CGU_BASE_SSP1_CLK_CLK_SEL(x) \
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((x) << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT)
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/* --- CGU_BASE_UART0_CLK values -------------------------------- */
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/* PD: Output stage power down */
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#define CGU_BASE_UART0_CLK_PD_SHIFT (0)
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#define CGU_BASE_UART0_CLK_PD (1 << CGU_BASE_UART0_CLK_PD_SHIFT)
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/* AUTOBLOCK: Block clock automatically during frequency change */
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#define CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT (11)
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#define CGU_BASE_UART0_CLK_AUTOBLOCK \
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(1 << CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT)
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/* CLK_SEL: Clock source selection */
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#define CGU_BASE_UART0_CLK_CLK_SEL_SHIFT (24)
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#define CGU_BASE_UART0_CLK_CLK_SEL_MASK \
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(0x1f << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT)
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#define CGU_BASE_UART0_CLK_CLK_SEL(x) \
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((x) << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT)
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/* --- CGU_BASE_UART1_CLK values -------------------------------- */
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/* PD: Output stage power down */
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#define CGU_BASE_UART1_CLK_PD_SHIFT (0)
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#define CGU_BASE_UART1_CLK_PD (1 << CGU_BASE_UART1_CLK_PD_SHIFT)
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/* AUTOBLOCK: Block clock automatically during frequency change */
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#define CGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT (11)
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#define CGU_BASE_UART1_CLK_AUTOBLOCK \
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(1 << CGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT)
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/* CLK_SEL: Clock source selection */
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#define CGU_BASE_UART1_CLK_CLK_SEL_SHIFT (24)
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#define CGU_BASE_UART1_CLK_CLK_SEL_MASK \
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(0x1f << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT)
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#define CGU_BASE_UART1_CLK_CLK_SEL(x) \
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((x) << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT)
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/* --- CGU_BASE_UART2_CLK values -------------------------------- */
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/* PD: Output stage power down */
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#define CGU_BASE_UART2_CLK_PD_SHIFT (0)
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#define CGU_BASE_UART2_CLK_PD (1 << CGU_BASE_UART2_CLK_PD_SHIFT)
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/* AUTOBLOCK: Block clock automatically during frequency change */
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#define CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT (11)
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#define CGU_BASE_UART2_CLK_AUTOBLOCK \
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(1 << CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT)
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/* CLK_SEL: Clock source selection */
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#define CGU_BASE_UART2_CLK_CLK_SEL_SHIFT (24)
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#define CGU_BASE_UART2_CLK_CLK_SEL_MASK \
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(0x1f << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT)
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#define CGU_BASE_UART2_CLK_CLK_SEL(x) \
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((x) << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT)
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/* --- CGU_BASE_UART3_CLK values -------------------------------- */
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/* PD: Output stage power down */
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#define CGU_BASE_UART3_CLK_PD_SHIFT (0)
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#define CGU_BASE_UART3_CLK_PD (1 << CGU_BASE_UART3_CLK_PD_SHIFT)
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/* AUTOBLOCK: Block clock automatically during frequency change */
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#define CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT (11)
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#define CGU_BASE_UART3_CLK_AUTOBLOCK \
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(1 << CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT)
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/* CLK_SEL: Clock source selection */
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#define CGU_BASE_UART3_CLK_CLK_SEL_SHIFT (24)
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#define CGU_BASE_UART3_CLK_CLK_SEL_MASK \
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(0x1f << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT)
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#define CGU_BASE_UART3_CLK_CLK_SEL(x) \
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((x) << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT)
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/* --- CGU_BASE_OUT_CLK values ---------------------------------- */
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/* PD: Output stage power down */
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#define CGU_BASE_OUT_CLK_PD_SHIFT (0)
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#define CGU_BASE_OUT_CLK_PD (1 << CGU_BASE_OUT_CLK_PD_SHIFT)
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/* AUTOBLOCK: Block clock automatically during frequency change */
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#define CGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT (11)
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#define CGU_BASE_OUT_CLK_AUTOBLOCK (1 << CGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT)
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/* CLK_SEL: Clock source selection */
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#define CGU_BASE_OUT_CLK_CLK_SEL_SHIFT (24)
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#define CGU_BASE_OUT_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT)
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#define CGU_BASE_OUT_CLK_CLK_SEL(x) ((x) << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT)
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/* --- CGU_BASE_APLL_CLK values --------------------------------- */
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/* PD: Output stage power down */
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#define CGU_BASE_APLL_CLK_PD_SHIFT (0)
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#define CGU_BASE_APLL_CLK_PD (1 << CGU_BASE_APLL_CLK_PD_SHIFT)
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/* AUTOBLOCK: Block clock automatically during frequency change */
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#define CGU_BASE_APLL_CLK_AUTOBLOCK_SHIFT (11)
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#define CGU_BASE_APLL_CLK_AUTOBLOCK (1 << CGU_BASE_APLL_CLK_AUTOBLOCK_SHIFT)
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/* CLK_SEL: Clock source selection */
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#define CGU_BASE_APLL_CLK_CLK_SEL_SHIFT (24)
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#define CGU_BASE_APLL_CLK_CLK_SEL_MASK \
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(0x1f << CGU_BASE_APLL_CLK_CLK_SEL_SHIFT)
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#define CGU_BASE_APLL_CLK_CLK_SEL(x) ((x) << CGU_BASE_APLL_CLK_CLK_SEL_SHIFT)
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/* --- CGU_BASE_CGU_OUT0_CLK values ----------------------------- */
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/* PD: Output stage power down */
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#define CGU_BASE_CGU_OUT0_CLK_PD_SHIFT (0)
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#define CGU_BASE_CGU_OUT0_CLK_PD (1 << CGU_BASE_CGU_OUT0_CLK_PD_SHIFT)
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/* AUTOBLOCK: Block clock automatically during frequency change */
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#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT (11)
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#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK \
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(1 << CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT)
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/* CLK_SEL: Clock source selection */
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#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT (24)
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#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_MASK \
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(0x1f << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT)
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#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL(x) \
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((x) << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT)
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/* --- CGU_BASE_CGU_OUT1_CLK values ----------------------------- */
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/* PD: Output stage power down */
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#define CGU_BASE_CGU_OUT1_CLK_PD_SHIFT (0)
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#define CGU_BASE_CGU_OUT1_CLK_PD (1 << CGU_BASE_CGU_OUT1_CLK_PD_SHIFT)
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/* AUTOBLOCK: Block clock automatically during frequency change */
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#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT (11)
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#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK \
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(1 << CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT)
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/* CLK_SEL: Clock source selection */
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#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT (24)
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#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_MASK \
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(0x1f << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT)
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#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL(x) \
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((x) << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT)
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/* --- CGU_BASE_x_CLK clock sources --------------------------------------- */
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#define CGU_SRC_32K 0x00
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#define CGU_SRC_IRC 0x01
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#define CGU_SRC_ENET_RX 0x02
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#define CGU_SRC_ENET_TX 0x03
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#define CGU_SRC_GP_CLKIN 0x04
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#define CGU_SRC_XTAL 0x06
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#define CGU_SRC_PLL0USB 0x07
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#define CGU_SRC_PLL0AUDIO 0x08
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#define CGU_SRC_PLL1 0x09
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#define CGU_SRC_IDIVA 0x0C
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#define CGU_SRC_IDIVB 0x0D
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#define CGU_SRC_IDIVC 0x0E
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#define CGU_SRC_IDIVD 0x0F
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#define CGU_SRC_IDIVE 0x10
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/**@}*/
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#endif
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