a2ee90fbfe
The stm32fx07 is common DesignWare IP, used in both STM32 and EFM32 chips. Rename the files to make this more clear, and easier to use in other targets.
106 lines
4.7 KiB
C
106 lines
4.7 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Gareth McMullin <gareth@blacksphere.co.nz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* This file covers definitions for DesignWare USB OTG HS peripherals.
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*/
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#ifndef LIBOPENCM3_USB_DWC_OTG_FS_H
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#define LIBOPENCM3_USB_DWC_OTG_FS_H
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/usb/dwc/otg_common.h>
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/* Memory map is required for USB_OTG_FS_BASE address */
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#if defined(STM32F1) || defined(STM32F2) || defined(STM32F4)
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# include <libopencm3/stm32/memorymap.h>
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#elif defined(EFM32HG)
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# include <libopencm3/efm32/memorymap.h>
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#else
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# error "device family not supported by dwc/otg_fs."
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#endif
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/***********************************************************************/
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/* Core Global Control and Status Registers */
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#define OTG_FS_GOTGCTL MMIO32(USB_OTG_FS_BASE + OTG_GOTGCTL)
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#define OTG_FS_GOTGINT MMIO32(USB_OTG_FS_BASE + OTG_GOTGINT)
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#define OTG_FS_GAHBCFG MMIO32(USB_OTG_FS_BASE + OTG_GAHBCFG)
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#define OTG_FS_GUSBCFG MMIO32(USB_OTG_FS_BASE + OTG_GUSBCFG)
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#define OTG_FS_GRSTCTL MMIO32(USB_OTG_FS_BASE + OTG_GRSTCTL)
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#define OTG_FS_GINTSTS MMIO32(USB_OTG_FS_BASE + OTG_GINTSTS)
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#define OTG_FS_GINTMSK MMIO32(USB_OTG_FS_BASE + OTG_GINTMSK)
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#define OTG_FS_GRXSTSR MMIO32(USB_OTG_FS_BASE + OTG_GRXSTSR)
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#define OTG_FS_GRXSTSP MMIO32(USB_OTG_FS_BASE + OTG_GRXSTSP)
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#define OTG_FS_GRXFSIZ MMIO32(USB_OTG_FS_BASE + OTG_GRXFSIZ)
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#define OTG_FS_GNPTXFSIZ MMIO32(USB_OTG_FS_BASE + OTG_GNPTXFSIZ)
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#define OTG_FS_GNPTXSTS MMIO32(USB_OTG_FS_BASE + OTG_GNPTXSTS)
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#define OTG_FS_GCCFG MMIO32(USB_OTG_FS_BASE + OTG_GCCFG)
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#define OTG_FS_CID MMIO32(USB_OTG_FS_BASE + OTG_CID)
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#define OTG_FS_HPTXFSIZ MMIO32(USB_OTG_FS_BASE + OTG_HPTXFSIZ)
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#define OTG_FS_DIEPTXF(x) MMIO32(USB_OTG_FS_BASE + OTG_DIEPTXF(x))
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/* Host-mode Control and Status Registers */
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#define OTG_FS_HCFG MMIO32(USB_OTG_FS_BASE + OTG_HCFG)
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#define OTG_FS_HFIR MMIO32(USB_OTG_FS_BASE + OTG_HFIR)
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#define OTG_FS_HFNUM MMIO32(USB_OTG_FS_BASE + OTG_HFNUM)
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#define OTG_FS_HPTXSTS MMIO32(USB_OTG_FS_BASE + OTG_HPTXSTS)
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#define OTG_FS_HAINT MMIO32(USB_OTG_FS_BASE + OTG_HAINT)
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#define OTG_FS_HAINTMSK MMIO32(USB_OTG_FS_BASE + OTG_HAINTMSK)
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#define OTG_FS_HPRT MMIO32(USB_OTG_FS_BASE + OTG_HPRT)
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#define OTG_FS_HCCHAR(x) MMIO32(USB_OTG_FS_BASE + OTG_HCCHAR(x))
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#define OTG_FS_HCINT(x) MMIO32(USB_OTG_FS_BASE + OTG_HCINT(x))
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#define OTG_FS_HCINTMSK(x) MMIO32(USB_OTG_FS_BASE + OTG_HCINTMSK(x))
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#define OTG_FS_HCTSIZ(x) MMIO32(USB_OTG_FS_BASE + OTG_HCTSIZ(x))
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/* Device-mode Control and Status Registers */
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#define OTG_FS_DCFG MMIO32(USB_OTG_FS_BASE + OTG_DCFG)
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#define OTG_FS_DCTL MMIO32(USB_OTG_FS_BASE + OTG_DCTL)
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#define OTG_FS_DSTS MMIO32(USB_OTG_FS_BASE + OTG_DSTS)
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#define OTG_FS_DIEPMSK MMIO32(USB_OTG_FS_BASE + OTG_DIEPMSK)
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#define OTG_FS_DOEPMSK MMIO32(USB_OTG_FS_BASE + OTG_DOEPMSK)
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#define OTG_FS_DAINT MMIO32(USB_OTG_FS_BASE + OTG_DAINT)
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#define OTG_FS_DAINTMSK MMIO32(USB_OTG_FS_BASE + OTG_DAINTMSK)
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#define OTG_FS_DVBUSDIS MMIO32(USB_OTG_FS_BASE + OTG_DVBUSDIS)
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#define OTG_FS_DVBUSPULSE MMIO32(USB_OTG_FS_BASE + OTG_DVBUSPULSE)
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#define OTG_FS_DIEPEMPMSK MMIO32(USB_OTG_FS_BASE + OTG_DIEPEMPMSK)
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#define OTG_FS_DIEPCTL0 MMIO32(USB_OTG_FS_BASE + OTG_DIEPCTL0)
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#define OTG_FS_DIEPCTL(x) MMIO32(USB_OTG_FS_BASE + OTG_DIEPCTL(x))
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#define OTG_FS_DOEPCTL0 MMIO32(USB_OTG_FS_BASE + OTG_DOEPCTL0)
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#define OTG_FS_DOEPCTL(x) MMIO32(USB_OTG_FS_BASE + OTG_DOEPCTL(x))
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#define OTG_FS_DIEPINT(x) MMIO32(USB_OTG_FS_BASE + OTG_DIEPINT(x))
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#define OTG_FS_DOEPINT(x) MMIO32(USB_OTG_FS_BASE + OTG_DOEPINT(x))
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#define OTG_FS_DIEPTSIZ0 MMIO32(USB_OTG_FS_BASE + OTG_DIEPTSIZ0)
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#define OTG_FS_DOEPTSIZ0 MMIO32(USB_OTG_FS_BASE + OTG_DOEPTSIZ0)
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#define OTG_FS_DIEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + OTG_DIEPTSIZ(x))
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#define OTG_FS_DTXFSTS(x) MMIO32(USB_OTG_FS_BASE + OTG_DTXFSTS(x))
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#define OTG_FS_DOEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + OTG_DOEPTSIZ(x))
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/* Power and clock gating control and status register */
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#define OTG_FS_PCGCCTL MMIO32(USB_OTG_FS_BASE + OTG_PCGCCTL)
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/* Data FIFO */
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#define OTG_FS_FIFO(x) (&MMIO32(USB_OTG_FS_BASE \
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+ (((x) + 1) \
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<< 12)))
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#endif
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