2b1ddc8490
The original submitter of this squished everything into one series, and has not returned. The code mostly appears good, and review comments were followed for the most part. The project doesn't really maintain any testing or board farm for sam3/sam4 parts, so we're going to just trust our users. Reviewed-by: Karl Palsson <karlp@tweak.net.au> sam/4l: IRQ Configuration file (irq.json) sam/4l: Basic Memory Map. sam/4l: GPIO Defines. sam/4l: GPIO Functions Added everything that needed to compile the library: Makefile, Linker Script and common includes. sam/4l: SCIF function to start OSC. sam/4l: GPIO Enable/Disable and Multiplexing configuration functions. sam/4l: PLL Clock configuration. sam/4l: Peripheral clock configuration and basic USART support. sam: USART Character length configuration. sam/4l: Generic Clock configuration functions. sam/4l: Analog to Digital Converter Interface (ADCIFE) basic support.
134 lines
4.2 KiB
C
134 lines
4.2 KiB
C
/** @addtogroup scif
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*
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* @brief <b>Access functions for the SAM4 System Controf Interface (SCIF)</b>
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* @ingroup SAM4
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* LGPL License Terms @ref lgpl_license
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* @author @htmlonly © @endhtmlonly 2016
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* Maxim Sloyko <maxims@google.com>
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*
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/sam/scif.h>
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/** @brief Enable external oscillator.
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*
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* @param[in] mode enum osc_mode: Oscillator mode (which pins oscillator connected to).
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* @param[in] freq uint32_t: External Oscillator frequency, in Hertz. Must be 0.6MHz - 30MHz
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* @param[in] startup enum osc_startup: Oscillator start time in RCSYS clock cycles.
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*
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* @returns zero upon success.
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*/
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int scif_osc_enable(enum osc_mode mode, uint32_t freq, enum osc_startup startup)
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{
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uint8_t gain;
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const uint32_t kHz = 1000;
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const uint32_t MHz = 1000 * kHz;
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if (freq > 600 * kHz && freq <= 2 * MHz) {
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gain = 0;
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} else if (freq > 2 * MHz && freq <= 4 * MHz) {
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gain = 1;
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} else if (freq > 4 * MHz && freq <= 8 * MHz) {
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gain = 2;
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} else if (freq > 8 * MHz && freq <= 16 * MHz) {
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gain = 3;
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} else if (freq > 16 * MHz && freq <= 30 * MHz) {
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gain = 4;
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} else {
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return -1;
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}
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SCIF_UNLOCK = SCIF_OSCCTRL0_KEY;
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SCIF_OSCCTRL0 = mode | SCIF_OSCCTRL_OSCEN |
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(gain << SCIF_OSCCTRL_GAIN_SHIFT) | (startup << SCIF_OSCCTRL_STARTUP_SHIFT);
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while (!(SCIF_PCLKSR & SCIF_OSC0RDY));
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return 0;
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}
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/** @brief Configure and enable PLL clock.
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*
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* @param[in] delay uint8_t: Specifies the number of RCSYS clock cycles before
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* ISR.PLLLOCKn will be set after PLL has been written, or after PLL has
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* been automatically re-enabled after exiting a sleep mode.
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* @param[in] mul uint8_t: Multiply factor.
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* @param[in] div uint8_t: Division factor.These fields determine the ratio of
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* the PLL output frequency to the source oscillator frequency:
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* f_vco = (PLLMUL+1)/PLLDIV * f_ref if PLLDIV >0
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* f_vco = 2*(PLLMUL+1) * f_ref if PLLDIV = 0
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* Note that the PLLMUL field should always be greater than 1 or the
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* behavior of the PLL will be undefined.
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* @param[in] pll_opt uint8_t: PLL Options.
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* @param[in] pll_opt uint8_t: PLL Options.
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*
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* @returns zero upon success.
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*/
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int scif_enable_pll(uint8_t delay, uint8_t mul, uint8_t div, uint8_t pll_opt, enum pll_clk_src source_clock)
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{
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// First, PLL needs to be disabled, otherwise the configuration register
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// is unaccessible.
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uint32_t pll_val = SCIF_PLL0;
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if (pll_val & SCIF_PLL0_PLLEN) {
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SCIF_UNLOCK = SCIF_PLL0_KEY;
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SCIF_PLL0 = pll_val & (~SCIF_PLL0_PLLEN);
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}
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if (mul == 0)
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mul = 1;
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pll_val = SCIF_PLL0_PLLOSC_MASKED(source_clock)
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| SCIF_PLL0_PLLOPT_MASKED(pll_opt)
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| SCIF_PLL0_PLLDIV_MASKED(div)
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| SCIF_PLL0_PLLMUL_MASKED(mul)
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| SCIF_PLL0_PLLCOUNT_MASKED(delay);
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SCIF_UNLOCK = SCIF_PLL0_KEY;
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SCIF_PLL0 = pll_val;
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// Now enable TODO: does this really need to be separate operation?
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SCIF_UNLOCK = SCIF_PLL0_KEY;
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SCIF_PLL0 = pll_val | SCIF_PLL0_PLLEN;
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while(!(SCIF_PCLKSR & SCIF_PLL0LOCK));
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return 0;
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}
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/** @brief Configure and enable Generic Clock
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*
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* @param[in] gclk enum generic_clock: Generic Clock to configure and enable.
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* @param[in] source_clock enum gclk_src: Source Clock for this Generic Clock.
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* @param[in] div uint16_t: Division Factor. Upper 8 bits only used for Generic Clock 11,
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* If 0, clock is undivided.
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*/
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void scif_enable_gclk(enum generic_clock gclk, enum gclk_src source_clock, uint16_t div)
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{
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uint32_t reg_val = SCIF_GCCTRL_CEN | SCIF_GCCTRL_OSCSEL_MASKED(source_clock);
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if (div) {
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if (gclk < GENERIC_CLOCK11) {
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div &= 0xf;
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}
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reg_val |= SCIF_GCCTRL_DIV_MASKED(div) | SCIF_GCCTRL_DIVEN;
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}
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SCIF_GCTRL(gclk) = reg_val;
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}
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