118 lines
5.0 KiB
C
118 lines
5.0 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2015 Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_EFM32_MEMORYMAP_H
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#define LIBOPENCM3_EFM32_MEMORYMAP_H
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#include <libopencm3/cm3/memorymap.h>
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#define PERIPH_BASE (0x40000000U)
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/* Device information */
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#define DI_BASE (0x0FE08000U)
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/* all names are "DI_" + <reg> */
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#define DI_CMU_LFRCOCTRL MMIO32(DI_BASE + 0x020)
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#define DI_CMU_HFRCOCTRL MMIO32(DI_BASE + 0x028)
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#define DI_CMU_AUXHFRCOCTRL MMIO32(DI_BASE + 0x030)
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#define DI_ADC0_CAL MMIO32(DI_BASE + 0x040)
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#define DI_ADC0_BIASPROG MMIO32(DI_BASE + 0x048)
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#define DI_DAC0_CAL MMIO32(DI_BASE + 0x050)
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#define DI_DAC0_BIASPROG MMIO32(DI_BASE + 0x058)
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#define DI_ACMP0_CTRL MMIO32(DI_BASE + 0x060)
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#define DI_ACMP1_CTRL MMIO32(DI_BASE + 0x068)
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#define DI_CMU_LCDCTRL MMIO32(DI_BASE + 0x078)
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#define DI_DAC0_OPACTRL MMIO32(DI_BASE + 0x0A0)
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#define DI_DAC0_OPAOFFSET MMIO32(DI_BASE + 0x0A8)
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#define DI_EMU_BUINACT MMIO32(DI_BASE + 0x0B0)
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#define DI_EMU_BUACT MMIO32(DI_BASE + 0x0B8)
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#define DI_EMU_BUBODBUVINCAL MMIO32(DI_BASE + 0x0C0)
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#define DI_EMU_BUBODUNREGCAL MMIO32(DI_BASE + 0x0C8)
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#define DI_DI_CRC MMIO16(DI_BASE + 0x1B0)
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#define DI_CAL_TEMP_0 MMIO8(DI_BASE + 0x1B2)
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#define DI_ADC0_CAL_1V25 MMIO16(DI_BASE + 0x1B4)
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#define DI_ADC0_CAL_2V5 MMIO16(DI_BASE + 0x1B6)
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#define DI_ADC0_CAL_VDD MMIO16(DI_BASE + 0x1B8)
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#define DI_ADC0_CAL_5VDIFF MMIO16(DI_BASE + 0x1BA)
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#define DI_ADC0_CAL_2XVDD MMIO16(DI_BASE + 0x1BC)
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#define DI_ADC0_TEMP_0_READ_1V25 MMIO16(DI_BASE + 0x1BE)
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#define DI_DAC0_CAL_1V25 MMIO32(DI_BASE + 0x1C8)
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#define DI_DAC0_CAL_2V5 MMIO32(DI_BASE + 0x1CC)
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#define DI_DAC0_CAL_VDD MMIO32(DI_BASE + 0x1D0)
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#define DI_AUXHFRCO_CALIB_BAND_1 MMIO8(DI_BASE + 0x1D4)
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#define DI_AUXHFRCO_CALIB_BAND_7 MMIO8(DI_BASE + 0x1D5)
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#define DI_AUXHFRCO_CALIB_BAND_11 MMIO8(DI_BASE + 0x1D6)
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#define DI_AUXHFRCO_CALIB_BAND_14 MMIO8(DI_BASE + 0x1D7)
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#define DI_AUXHFRCO_CALIB_BAND_21 MMIO8(DI_BASE + 0x1D8)
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#define DI_AUXHFRCO_CALIB_BAND_28 MMIO8(DI_BASE + 0x1D9)
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#define DI_HFRCO_CALIB_BAND_1 MMIO8(DI_BASE + 0x1DC)
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#define DI_HFRCO_CALIB_BAND_7 MMIO8(DI_BASE + 0x1DD)
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#define DI_HFRCO_CALIB_BAND_11 MMIO8(DI_BASE + 0x1DE)
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#define DI_HFRCO_CALIB_BAND_14 MMIO8(DI_BASE + 0x1DF)
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#define DI_HFRCO_CALIB_BAND_21 MMIO8(DI_BASE + 0x1E0)
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#define DI_HFRCO_CALIB_BAND_28 MMIO8(DI_BASE + 0x1E1)
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#define DI_MEM_INFO_PAGE_SIZE MMIO8(DI_BASE + 0x1E7)
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#define DI_UNIQUE_0 MMIO32(DI_BASE + 0x1F0)
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#define DI_UNIQUE_1 MMIO32(DI_BASE + 0x1F4)
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#define DI_MEM_INFO_FLASH MMIO16(DI_BASE + 0x1F8)
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#define DI_MEM_INFO_RAM MMIO16(DI_BASE + 0x1FA)
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#define DI_PART_NUMBER MMIO16(DI_BASE + 0x1FC)
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#define DI_PART_FAMILY MMIO8(DI_BASE + 0x1FE)
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#define DI_PROD_REV MMIO8(DI_BASE + 0x1FF)
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#define AES_BASE (PERIPH_BASE + 0xE0000)
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#define PRS_BASE (PERIPH_BASE + 0xCC000)
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#define RMU_BASE (PERIPH_BASE + 0xCA000)
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#define CMU_BASE (PERIPH_BASE + 0xC8000)
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#define EMU_BASE (PERIPH_BASE + 0xC6000)
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#define USB_BASE (PERIPH_BASE + 0xC4000)
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#define DMA_BASE (PERIPH_BASE + 0xC2000)
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#define MSC_BASE (PERIPH_BASE + 0xC0000)
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#define LESENSE_BASE (PERIPH_BASE + 0x8C000)
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#define LCD_BASE (PERIPH_BASE + 0x8A000)
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#define WDOG_BASE (PERIPH_BASE + 0x88000)
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#define PCNT2_BASE (PERIPH_BASE + 0x86800)
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#define PCNT1_BASE (PERIPH_BASE + 0x86400)
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#define PCNT0_BASE (PERIPH_BASE + 0x86000)
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#define LEUART1_BASE (PERIPH_BASE + 0x84400)
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#define LEUART0_BASE (PERIPH_BASE + 0x84000)
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#define LETIMER0_BASE (PERIPH_BASE + 0x82000)
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#define BURTC_BASE (PERIPH_BASE + 0x81000)
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#define RTC_BASE (PERIPH_BASE + 0x80000)
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#define TIMER3_BASE (PERIPH_BASE + 0x10C00)
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#define TIMER2_BASE (PERIPH_BASE + 0x10800)
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#define TIMER1_BASE (PERIPH_BASE + 0x10400)
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#define TIMER0_BASE (PERIPH_BASE + 0x10000)
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#define UART1_BASE (PERIPH_BASE + 0x0E400)
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#define UART0_BASE (PERIPH_BASE + 0x0E000)
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#define USART2_BASE (PERIPH_BASE + 0x0C800)
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#define USART1_BASE (PERIPH_BASE + 0x0C400)
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#define USART0_BASE (PERIPH_BASE + 0x0C000)
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#define I2C1_BASE (PERIPH_BASE + 0x0A400)
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#define I2C0_BASE (PERIPH_BASE + 0x0A000)
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#define EBI_BASE (PERIPH_BASE + 0x08000)
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#define GPIO_BASE (PERIPH_BASE + 0x06000)
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#define DAC0_BASE (PERIPH_BASE + 0x04000)
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#define ADC0_BASE (PERIPH_BASE + 0x02000)
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#define ACMP1_BASE (PERIPH_BASE + 0x01400)
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#define ACMP0_BASE (PERIPH_BASE + 0x01000)
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#define VCMP_BASE (PERIPH_BASE + 0x00000)
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#endif
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