c9857ad52a
Extend the clock controller module with a function to calculate core clocks from the current registers settings. On Vybrid, we assume that the core clocks are setup by the main operating system running on the Cortex-A5. Nevertheless we need to know their actual values in order to calculate other clocks or baud rates. Verified on a Colibri VF61, which calculates following values: ccm_core_clk: 500210526 ccm_platform_bus_clk: 166736842 ccm_ipg_bus_clk: 83368421
56 lines
1.8 KiB
C
56 lines
1.8 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2014 Stefan Agner <stefan@agner.ch>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_MEMORYMAP_H
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#define LIBOPENCM3_MEMORYMAP_H
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#include <libopencm3/cm3/memorymap.h>
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/* --- VF6xx specific peripheral definitions ----------------------------- */
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/* Memory map for all busses */
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#define PERIPH_BASE (0x40000000U)
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#define PERIPH_BASE_AIPS0 (PERIPH_BASE + 0x00000)
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#define PERIPH_BASE_AIPS1 (PERIPH_BASE + 0x80000)
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/* Pheripheral addresses */
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/* AIPS0 */
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#define MSCM_BASE (PERIPH_BASE_AIPS0 + 0x01000)
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#define SEMA4_BASE (PERIPH_BASE_AIPS0 + 0x1D000)
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#define UART0_BASE (PERIPH_BASE_AIPS0 + 0x27000)
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#define UART1_BASE (PERIPH_BASE_AIPS0 + 0x28000)
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#define UART2_BASE (PERIPH_BASE_AIPS0 + 0x29000)
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#define UART3_BASE (PERIPH_BASE_AIPS0 + 0x2A000)
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#define SPI0_BASE (PERIPH_BASE_AIPS0 + 0x2C000)
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#define SPI1_BASE (PERIPH_BASE_AIPS0 + 0x2D000)
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#define ANADIG_BASE (PERIPH_BASE_AIPS0 + 0x50000)
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#define CCM_BASE (PERIPH_BASE_AIPS0 + 0x6B000)
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/* AIPS1 */
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#define UART4_BASE (PERIPH_BASE_AIPS1 + 0x29000)
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#define UART5_BASE (PERIPH_BASE_AIPS1 + 0x2A000)
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#endif
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