79 lines
2.8 KiB
C
79 lines
2.8 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_SYSCFG_H
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#define LIBOPENCM3_SYSCFG_H
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/stm32/memorymap.h>
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/* --- SYSCFG registers ---------------------------------------------------- */
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#define SYSCFG_CFGR1 MMIO32(SYSCFG_COMP_BASE + 0x00)
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#define SYSCFG_EXTICR(i) MMIO32(SYSCFG_COMP_BASE + 0x08 + (i)*4)
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#define SYSCFG_EXTICR1 SYSCFG_EXTICR(0)
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#define SYSCFG_EXTICR2 SYSCFG_EXTICR(1)
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#define SYSCFG_EXTICR3 SYSCFG_EXTICR(2)
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#define SYSCFG_EXTICR4 SYSCFG_EXTICR(3)
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#define SYSCFG_CFGR2 MMIO32(SYSCFG_COMP_BASE + 0x18)
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/* Register values ----------------------------------------------------------*/
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/* SYSCFG_CFGR1 Values -- ---------------------------------------------------*/
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#define SYSCFG_CFGR1_MEM_MODE_SHIFT 0
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#define SYSCFG_CFGR1_MEM_MODE (3 << SYSCFG_CFGR1_MEM_MODE_SHIFT)
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#define SYSCFG_CFGR1_MEM_MODE_FLASH (0 << SYSCFG_CFGR1_MEM_MODE_SHIFT)
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#define SYSCFG_CFGR1_MEM_MODE_SYSTEM (1 << SYSCFG_CFGR1_MEM_MODE_SHIFT)
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#define SYSCFG_CFGR1_MEM_MODE_SRAM (3 << SYSCFG_CFGR1_MEM_MODE_SHIFT)
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#define SYSCFG_CFGR1_ADC_DMA_RMP (1 << 8)
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#define SYSCFG_CFGR1_USART1_TX_DMA_RMP (1 << 9)
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#define SYSCFG_CFGR1_USART1_RX_DMA_RMP (1 << 10)
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#define SYSCFG_CFGR1_TIM16_DMA_RMP (1 << 11)
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#define SYSCFG_CFGR1_TIM17_DMA_RMP (1 << 12)
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#define SYSCFG_CFGR1_I2C_PB6_FMPLUS (1 << 16)
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#define SYSCFG_CFGR1_I2C_PB7_FMPLUS (1 << 17)
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#define SYSCFG_CFGR1_I2C_PB8_FMPLUS (1 << 18)
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#define SYSCFG_CFGR1_I2C_PB9_FMPLUS (1 << 19)
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#define SYSCFG_CFGR1_I2C1_FMPLUS (1 << 20)
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#define SYSCFG_CFGR1_I2C_PA9_FMPLUS (1 << 22)
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#define SYSCFG_CFGR1_I2C_PA10_FMPLUS (1 << 23)
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#define SYSCFG_EXTICR_SKIP 4
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#define SYSCFG_EXTICR_GPIOA 0
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#define SYSCFG_EXTICR_GPIOB 1
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#define SYSCFG_EXTICR_GPIOC 2
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#define SYSCFG_EXTICR_GPIOD 3
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#define SYSCFG_EXTICR_GPIOF 5
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#define SYSCFG_CFGR2_LOCKUP_LOCK (1 << 0)
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#define SYSCFG_CFGR2_SRAM_PARITY_LOCK (1 << 1)
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#define SYSCFG_CFGR2_PVD_LOCK (1 << 2)
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#define SYSCFG_CFGR2_SRAM_PEF (1 << 8)
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/* API values ---------------------------------------------------------------*/
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BEGIN_DECLS
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END_DECLS
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#endif
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