101 lines
2.9 KiB
C
101 lines
2.9 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Gareth McMullin <gareth@blacksphere.co.nz>
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* Copyright (C) 2015 Felix Held <felix-libopencm3@felixheld.de>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#if defined(LIBOPENCM3_PMC_H)
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#ifndef LIBOPENCM3_PMC_COMMON_3A3U3X_H
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#define LIBOPENCM3_PMC_COMMON_3A3U3X_H
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/* --- Power Management Controller (PMC) registers ----------------------- */
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/* UTMI Clock Register */
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#define CKGR_UCKR MMIO32(PMC_BASE + 0x001C)
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/* --- Register contents --------------------------------------------------- */
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/* --- PMC UTMI Clock Configuration Register (CKGR_UCKR) ------------------- */
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/* UTMI PLL Start-up Time */
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#define CKGR_UCKR_UPLLCOUNT_SHIFT 20
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#define CKGR_UCKR_UPLLCOUNT_MASK (0x0F << CKGR_UCKR_UPLLCOUNT_SHIFT)
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/* UTMI PLL Enable */
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#define CKGR_UCKR_UPLLEN (0x01 << 16)
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/* --- PMC Master Clock Register (PMC_MCKR) -------------------------------- */
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/* UPLL Divide by 2 */
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#define PMC_MCKR_UPLLDIV2 (0x01 << 13)
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/* Master Clock Source Selection */
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#define PMC_MCKR_CSS_UPLL_CLK (3 << PMC_MCKR_CSS_SHIFT)
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/* --- PMC Programmable Clock Register 0 (PMC_PCK0) ------------------------ */
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/* Master Clock Source Selection */
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#define PMC_PCK0_CSS_UPLL_CLK (3 << PMC_PCK0_CSS_SHIFT)
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/* --- PMC Programmable Clock Register 1 (PMC_PCK1) ------------------------ */
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/* Master Clock Source Selection */
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#define PMC_PCK1_CSS_UPLL_CLK (3 << PMC_PCK1_CSS_SHIFT)
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/* --- PMC Programmable Clock Register 2 (PMC_PCK2) ------------------------ */
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/* Master Clock Source Selection */
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#define PMC_PCK2_CSS_UPLL_CLK (3 << PMC_PCK2_CSS_SHIFT)
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/* --- PMC Interrupt Enable Register (PMC_IER) ----------------------------- */
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/* UTMI PLL Lock Interrupt Enable */
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#define PMC_IER_LOCKU (0x01 << 6)
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/* --- PMC Interrupt Disable Register (PMC_IDR) ----------------------------- */
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/* UTMI PLL Lock Interrupt Disable */
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#define PMC_IDR_LOCKU (0x01 << 6)
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/* --- PMC Status Register (PMC_SR) ---------------------------------------- */
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/* UTMI PLL Lock Status */
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#define PMC_SR_LOCKU (0x01 << 6)
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/* --- PMC Interrupt Mask Register (PMC_IMR) ----------------------------- */
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/* UTMI PLL Lock Interrupt Mask */
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#define PMC_IMR_LOCKU (0x01 << 6)
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#endif
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#else
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#warning "pmc_common_3a3u3x.h should not be included explicitly, only via pmc.h"
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#endif
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