167 lines
5.9 KiB
C
167 lines
5.9 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LPC43XX_CGU_H
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#define CGU_LPC43XX_CGU_H
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/lpc43xx/memorymap.h>
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/* --- CGU registers ------------------------------------------------------- */
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/* Frequency monitor register */
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#define CGU_FREQ_MON MMIO32(CGU_BASE + 0x014)
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/* Crystal oscillator control register */
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#define CGU_XTAL_OSC_CTRL MMIO32(CGU_BASE + 0x018)
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/* PLL0USB status register */
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#define CGU_PLL0USB_STAT MMIO32(CGU_BASE + 0x01C)
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/* PLL0USB control register */
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#define CGU_PLL0USB_CTRL MMIO32(CGU_BASE + 0x020)
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/* PLL0USB M-divider register */
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#define CGU_PLL0USB_MDIV MMIO32(CGU_BASE + 0x024)
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/* PLL0USB N/P-divider register */
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#define CGU_PLL0USB_NP_DIV MMIO32(CGU_BASE + 0x028)
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/* PLL0AUDIO status register */
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#define CGU_PLL0AUDIO_STAT MMIO32(CGU_BASE + 0x02C)
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/* PLL0AUDIO control register */
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#define CGU_PLL0AUDIO_CTRL MMIO32(CGU_BASE + 0x030)
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/* PLL0AUDIO M-divider register */
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#define CGU_PLL0AUDIO_MDIV MMIO32(CGU_BASE + 0x034)
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/* PLL0AUDIO N/P-divider register */
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#define CGU_PLL0AUDIO_NP_DIV MMIO32(CGU_BASE + 0x038)
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/* PLL0AUDIO fractional divider register */
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#define CGU_PLLAUDIO_FRAC MMIO32(CGU_BASE + 0x03C)
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/* PLL1 status register */
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#define CGU_PLL1_STAT MMIO32(CGU_BASE + 0x040)
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/* PLL1 control register */
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#define CGU_PLL1_CTRL MMIO32(CGU_BASE + 0x044)
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/* Integer divider A control register */
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#define CGU_IDIVA_CTRL MMIO32(CGU_BASE + 0x048)
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/* Integer divider B control register */
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#define CGU_IDIVB_CTRL MMIO32(CGU_BASE + 0x04C)
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/* Integer divider C control register */
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#define CGU_IDIVC_CTRL MMIO32(CGU_BASE + 0x050)
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/* Integer divider D control register */
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#define CGU_IDIVD_CTRL MMIO32(CGU_BASE + 0x054)
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/* Integer divider E control register */
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#define CGU_IDIVE_CTRL MMIO32(CGU_BASE + 0x058)
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/* Output stage 0 control register */
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#define CGU_BASE_SAFE_CLK MMIO32(CGU_BASE + 0x05C)
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/* Output stage 1 control register for base clock */
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#define CGU_BASE_USB0_CLK MMIO32(CGU_BASE + 0x060)
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/* Output stage 2 control register for base clock */
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#define CGU_BASE_PERIPH_CLK MMIO32(CGU_BASE + 0x064)
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/* Output stage 3 control register for base clock */
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#define CGU_BASE_USB1_CLK MMIO32(CGU_BASE + 0x068)
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/* Output stage 4 control register for base clock */
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#define CGU_BASE_M4_CLK MMIO32(CGU_BASE + 0x06C)
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/* Output stage 5 control register for base clock */
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#define CGU_BASE_SPIFI_CLK MMIO32(CGU_BASE + 0x070)
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/* Output stage 6 control register for base clock */
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#define CGU_BASE_SPI_CLK MMIO32(CGU_BASE + 0x074)
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/* Output stage 7 control register for base clock */
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#define CGU_BASE_PHY_RX_CLK MMIO32(CGU_BASE + 0x078)
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/* Output stage 8 control register for base clock */
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#define CGU_BASE_PHY_TX_CLK MMIO32(CGU_BASE + 0x07C)
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/* Output stage 9 control register for base clock */
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#define CGU_BASE_APB1_CLK MMIO32(CGU_BASE + 0x080)
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/* Output stage 10 control register for base clock */
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#define CGU_BASE_APB3_CLK MMIO32(CGU_BASE + 0x084)
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/* Output stage 11 control register for base clock */
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#define CGU_BASE_LCD_CLK MMIO32(CGU_BASE + 0x088)
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/* Output stage 12 control register for base clock */
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#define CGU_BASE_VADC_CLK MMIO32(CGU_BASE + 0x08C)
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/* Output stage 13 control register for base clock */
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#define CGU_BASE_SDIO_CLK MMIO32(CGU_BASE + 0x090)
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/* Output stage 14 control register for base clock */
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#define CGU_BASE_SSP0_CLK MMIO32(CGU_BASE + 0x094)
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/* Output stage 15 control register for base clock */
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#define CGU_BASE_SSP1_CLK MMIO32(CGU_BASE + 0x098)
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/* Output stage 16 control register for base clock */
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#define CGU_BASE_UART0_CLK MMIO32(CGU_BASE + 0x09C)
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/* Output stage 17 control register for base clock */
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#define CGU_BASE_UART1_CLK MMIO32(CGU_BASE + 0x0A0)
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/* Output stage 18 control register for base clock */
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#define CGU_BASE_UART2_CLK MMIO32(CGU_BASE + 0x0A4)
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/* Output stage 19 control register for base clock */
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#define CGU_BASE_UART3_CLK MMIO32(CGU_BASE + 0x0A8)
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/* Output stage 20 control register for base clock */
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#define CGU_BASE_OUT_CLK MMIO32(CGU_BASE + 0x0AC)
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/* Reserved output stage */
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#define CGU_OUTCLK_21_CTRL MMIO32(CGU_BASE + 0x0B0)
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/* Reserved output stage */
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#define CGU_OUTCLK_22_CTRL MMIO32(CGU_BASE + 0x0B4)
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/* Reserved output stage */
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#define CGU_OUTCLK_23_CTRL MMIO32(CGU_BASE + 0x0B8)
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/* Reserved output stage */
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#define CGU_OUTCLK_24_CTRL MMIO32(CGU_BASE + 0x0BC)
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/* Output stage 25 control register for base clock */
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#define CGU_BASE_APLL_CLK MMIO32(CGU_BASE + 0x0C0)
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/* Output stage 26 control CLK register for base clock */
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#define CGU_BASE_CGU_OUT0_CLK MMIO32(CGU_BASE + 0x0C4)
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/* Output stage 27 control CLK register for base clock */
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#define CGU_BASE_CGU_OUT1_CLK MMIO32(CGU_BASE + 0x0C8)
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#endif
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