d84c4030b2
Now all examples are including only the modules they really need. Also each header file of the library is including only the necessary headers making it possible to use these modules in parallel with other implementations that may collide with the definitions in other modules.
118 lines
4.2 KiB
C
118 lines
4.2 KiB
C
/*
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* This file is part of the libopenstm32 project.
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*
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* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENSTM32_NVIC_H
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#define LIBOPENSTM32_NVIC_H
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#include <libopenstm32/memorymap.h>
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#include <libopenstm32/common.h>
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/* --- NVIC Registers ------------------------------------------------------ */
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/* ISER: Interrupt Set Enable Registers */
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/* Note: 8 32bit Registers */
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#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4))
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/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */
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/* ICER: Interrupt Clear Enable Registers */
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/* Note: 8 32bit Registers */
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#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4))
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/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */
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/* ISPR: Interrupt Set Priority Registers */
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/* Note: 8 32bit Registers */
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#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4))
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/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */
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/* ICPR: Interrupt Clear Priority Registers */
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/* Note: 8 32bit Registers */
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#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4))
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/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */
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/* IABR: Interrupt Active Bit Register */
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/* Note: 8 32bit Registers */
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#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4))
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/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */
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/* IPR: Interrupt Priority Registers */
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/* Note: 240 8bit Registers */
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#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id)
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/* STIR: Software Trigger Interrupt Register */
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#define NVIC_STIR MMIO32(STIR_BASE)
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/* --- SCB: Registers ------------------------------------------------------ */
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/* CPUID: CPUID base register */
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#define SCB_CPUID MMIO32(SCB_BASE + 0x00)
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/* ICSR: Interrupt Control State Register */
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#define SCB_ICSR MMIO32(SCB_BASE + 0x04)
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/* VTOR: Vector Table Offset Register */
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#define SCB_VTOR MMIO32(SCB_BASE + 0x08)
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/* AIRCR: Application Interrupt and Reset Control Register */
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#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C)
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/* SCR: System Control Register */
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#define SCB_SCR MMIO32(SCB_BASE + 0x10)
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/* CCR: Configuration Control Register */
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#define SCB_CCR MMIO32(SCB_BASE + 0x14)
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/* SHP: System Handler Priority Registers */
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/* Note: 12 8bit registers */
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#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id)
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/* SHCSR: System Handler Control and State Register */
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#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
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/* CFSR: Configurable Fault Status Registers */
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#define SCB_CFSR MMIO32(SCB_BASE + 0x28)
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/* HFSR: Hard Fault Status Register */
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#define SCB_HFSR MMIO32(SCB_BASE + 0x2C)
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/* DFSR: Debug Fault Status Register */
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#define SCB_DFSR MMIO32(SCB_BASE + 0x30)
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/* MMFAR: Memory Manage Fault Address Register */
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#define SCB_MMFAR MMIO32(SCB_BASE + 0x34)
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/* BFAR: Bus Fault Address Register */
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#define SCB_BFAR MMIO32(SCB_BASE + 0x38)
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/* AFSR: Auxiliary Fault Status Register */
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#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
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/* --- NVIC functions ------------------------------------------------------ */
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void nvic_enable_irq(s32 irqn);
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void nvic_disable_irq(s32 irqn);
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s32 nvic_get_pending_irq(s32 irqn);
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void nvic_set_pending_irq(s32 irqn);
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void nvic_clear_pending_irq(s32 irqn);
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s32 nvic_get_active(s32 irqn);
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#endif
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