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For ARMv6M, the IPR and SHPR registers are accessible only when adddressed with a 32bit word read or write. Currently in libopencm3 all NVIC interrupt priority register accesses are made using an 8bit read or write, which results in the hardware ignoring the write or always returning 0 on read. Address this by introducing NVIC_IPR32() and SCS_SHPR32() macro and conditional implementation of nvic_set_priority when building for cortex-m0. See ARMv6M developer documentation: IPR: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0497a/Cihgjeed.html SHPR: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0497a/CIAGECDD.html