239 lines
7.0 KiB
YAML
239 lines
7.0 KiB
YAML
copyright: "2012 chrysn <chrysn@fsfe.org>"
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license: lgpl-3+
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ingroup: EFM32TG
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shortdocname: EFM32TG_LCD
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shortname: LCD
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longname: Liquid Crystal Display driver
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baseref: d0034_efm32tg_reference_manual.pdf section 29
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registers_baserefext: ".4"
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templateregs:
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- name: I
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comment: Bits for the various LCD interrupt registers
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fields:
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- {name: FC, shift: 0}
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- name: SEG
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comment: Bits for the individual SEG pins
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override_backref: These values are used by the SEGDxL registers, as defined in d0034_efm32tg_reference_manual.pdf sections 29.5.12 to .15 and .18 to .21.
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fields:
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- {name: 23, shift: 23}
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- {name: 22, shift: 22}
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- {name: 21, shift: 21}
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- {name: 20, shift: 20}
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- {name: 19, shift: 19}
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- {name: 18, shift: 18}
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- {name: 17, shift: 17}
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- {name: 16, shift: 16}
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- {name: 15, shift: 15}
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- {name: 14, shift: 14}
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- {name: 13, shift: 13}
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- {name: 12, shift: 12}
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- {name: 11, shift: 11}
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- {name: 10, shift: 10}
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- {name: 9, shift: 9}
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- {name: 8, shift: 8}
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- {name: 7, shift: 7}
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- {name: 6, shift: 6}
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- {name: 5, shift: 5}
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- {name: 4, shift: 4}
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- {name: 3, shift: 3}
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- {name: 2, shift: 2}
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- {name: 1, shift: 1}
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- {name: 0, shift: 0}
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registers:
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- name: CTRL
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offset: 0x000
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definition_baserefext: .5.1
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fields:
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- name: DSC
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shift: 23
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- name: UDCTRL
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shift: 1
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length: 2
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values:
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- {name: REGULAR, value: 0}
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- {name: FCEVENT, value: 1}
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- {name: FRAMESTART, value: 2}
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- name: EN
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shift: 0
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- name: DISPCTRL
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offset: 0x004
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definition_baserefext: .5.2
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fields:
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# MUXE left out and defined manually at the end
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- name: VBLEV
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shift: 18
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length: 3
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values:
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- {name: LEVEL0, value: 0}
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- {name: LEVEL1, value: 1}
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- {name: LEVEL2, value: 2}
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- {name: LEVEL3, value: 3}
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- {name: LEVEL4, value: 4}
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- {name: LEVEL5, value: 5}
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- {name: LEVEL6, value: 6}
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- {name: LEVEL7, value: 7}
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- name: VLCDSEL
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shift: 16
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values:
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- {name: VDD, value: 0}
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- {name: VEXTBOOST, value: 1}
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- name: CONCONF
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shift: 15
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values:
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- {value: 0, name: VLCD}
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- {value: 1, name: GND}
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- name: CONLEV
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shift: 8
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length: 5
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type: uint
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doc: "By this parameter, the voltage V_LCD_OUT is interpolated linearly from 0.5V_LCD to V_LCD."
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- name: WAVE
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shift: 4
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values:
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- {value: 0, name: LOWPOWER}
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- {value: 1, name: NORMAL}
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- name: BIAS
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shift: 2
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length: 2
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values:
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- {value: 0, name: STATIC}
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- {value: 1, name: ONEHALF}
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- {value: 2, name: ONETHIRD}
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- {value: 3, name: ONEFOURTH}
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- name: MUX
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mask: "0x00400003"
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values:
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- {value: "0x00000000", name: STATIC}
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- {value: "0x00000001", name: DUPLEX}
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- {value: "0x00000002", name: TRIPLEX}
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- {value: "0x00000003", name: QUADRUPLEX}
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- {value: "0x00400001", name: SEXTAPLEX}
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- {value: "0x00400003", name: OCTAPLEX}
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doc: These definitions munge the MUX and the MUXE fields, as they are described in the documentation only together too.
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- name: SEGEN
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offset: 0x008
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definition_baserefext: .5.3
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# FIXME how do we reperesent this best?
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- name: BACTRL
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offset: 0x00c
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definition_baserefext: .5.4
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fields:
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- name: FCTOP
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shift: 18
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length: 6
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type: uint
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- name: FCPRESC
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shift: 16
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length: 2
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values:
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- {value: 0, name: DIV1}
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- {value: 1, name: DIV2}
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- {value: 2, name: DIV4}
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- {value: 3, name: DIV8}
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- name: FCEN
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shift: 8
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- name: ALGOSEL
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shift: 7
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values:
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- {value: 0, name: AND}
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- {value: 1, name: OR}
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- name: AREGBSC
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shift: 5
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length: 2
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values: &BACTRL_AREGBSC
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- {value: 0, name: NOSHIFT}
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- {value: 1, name: SHIFTLEFT}
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- {value: 2, name: SHIFTRIGHT}
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- name: AREGASC
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shift: 3
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length: 2
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values: *BACTRL_AREGBSC
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- name: AEN
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shift: 2
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- name: BLANK
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shift: 1
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- name: BLINKEN
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shift: 0
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- name: STATUS
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offset: 0x010
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definition_baserefext: .5.5
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fields:
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- name: BLINK
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shift: 8
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- name: ASTATE
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shift: 0
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length: 4
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type: uint
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- name: AREGA
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offset: 0x014
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# FIXME: how do we represent this in the header?
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- name: AREGB
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offset: 0x018
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# FIXME: how do we represent this in the header?
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- name: IF
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offset: 0x01c
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definition_baserefext: .5.8
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fields: I
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- name: IFS
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offset: 0x020
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definition_baserefext: .5.9
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fields: I
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- name: IFC
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offset: 0x024
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definition_baserefext: .5.10
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fields: I
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- name: IEN
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offset: 0x028
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definition_baserefext: .5.11
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fields: I
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- name: SEGD0L
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offset: 0x040
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fields: SEG
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- name: SEGD1L
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offset: 0x044
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fields: SEG
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- name: SEGD2L
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offset: 0x048
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fields: SEG
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- name: SEGD3L
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offset: 0x04c
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fields: SEG
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- name: FREEZE
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offset: 0x060
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definition_baserefext: .5.16
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fields:
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- name: REGFREEZE
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shift: 0
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values:
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- {value: 0, name: UPDATE}
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- {value: 1, name: FREEZE}
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# FIXME: this seems to be a typical FREEZE register
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- name: SYNGBUSY
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offset: 0x064
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definition_baserefext: .5.17
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fields:
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- {name: SEGD7L, shift: 19}
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- {name: SEGD6L, shift: 18}
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- {name: SEGD5L, shift: 17}
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- {name: SEGD4L, shift: 16}
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- {name: SEGD3L, shift: 7}
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- {name: SEGD2L, shift: 6}
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- {name: SEGD1L, shift: 5}
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- {name: SEGD0L, shift: 4}
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- {name: AREGB, shift: 3}
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- {name: AREGA, shift: 2}
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- {name: BACTRL, shift: 1}
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- {name: CTRL, shift: 0}
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- name: SEGD4L
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offset: 0x0CC
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fields: SEG
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- name: SEGD5L
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offset: 0x0D0
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fields: SEG
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- name: SEGD6L
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offset: 0x0D4
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fields: SEG
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- name: SEGD7L
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offset: 0x0D8
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fields: SEG
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