e2022f5884
to remove errors, duplications and inconsistencies. File lib/stm32/f1/pwr.c - all code removed as it duplicates that in common/pwr_common.c Remaining changes do not affect code. Compiles OK. TODO efm32 has no code so generates no modules TODO F2 needs pwr.c TODO L1 needs dma.h and dma.c
124 lines
3.5 KiB
C
124 lines
3.5 KiB
C
/** @addtogroup pwr_defines
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@author @htmlonly © @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA PWR.H */
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#ifndef LIBOPENCM3_PWR_COMMON_ALL_H
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#define LIBOPENCM3_PWR_COMMON_ALL_H
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/**@{*/
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#include <libopencm3/cm3/common.h>
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/* --- PWR registers ------------------------------------------------------- */
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/* Power control register (PWR_CR) */
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#define PWR_CR MMIO32(POWER_CONTROL_BASE + 0x00)
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/* Power control/status register (PWR_CSR) */
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#define PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04)
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/* --- PWR_CR values ------------------------------------------------------- */
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/* Bits [31:9]: Reserved, must be kept at reset value. */
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/* DBP: Disable backup domain write protection */
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#define PWR_CR_DBP (1 << 8)
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/* PLS[7:5]: PVD level selection */
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#define PWR_CR_PLS_LSB 5
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/** @defgroup pwr_pls PVD level selection
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@ingroup STM32F_pwr_defines
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@{*/
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#define PWR_CR_PLS_2V2 (0x0 << PWR_CR_PLS_LSB)
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#define PWR_CR_PLS_2V3 (0x1 << PWR_CR_PLS_LSB)
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#define PWR_CR_PLS_2V4 (0x2 << PWR_CR_PLS_LSB)
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#define PWR_CR_PLS_2V5 (0x3 << PWR_CR_PLS_LSB)
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#define PWR_CR_PLS_2V6 (0x4 << PWR_CR_PLS_LSB)
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#define PWR_CR_PLS_2V7 (0x5 << PWR_CR_PLS_LSB)
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#define PWR_CR_PLS_2V8 (0x6 << PWR_CR_PLS_LSB)
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#define PWR_CR_PLS_2V9 (0x7 << PWR_CR_PLS_LSB)
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/**@}*/
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#define PWR_CR_PLS_MASK (0x7 << PWR_CR_PLS_LSB)
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/* PVDE: Power voltage detector enable */
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#define PWR_CR_PVDE (1 << 4)
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/* CSBF: Clear standby flag */
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#define PWR_CR_CSBF (1 << 3)
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/* CWUF: Clear wakeup flag */
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#define PWR_CR_CWUF (1 << 2)
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/* PDDS: Power down deepsleep */
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#define PWR_CR_PDDS (1 << 1)
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/* LPDS: Low-power deepsleep */
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#define PWR_CR_LPDS (1 << 0)
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/* --- PWR_CSR values ------------------------------------------------------ */
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/* Bits [31:9]: Reserved, must be kept at reset value. */
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/* EWUP: Enable WKUP pin */
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#define PWR_CSR_EWUP (1 << 8)
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/* Bits [7:3]: Reserved, must be kept at reset value. */
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/* PVDO: PVD output */
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#define PWR_CSR_PVDO (1 << 2)
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/* SBF: Standby flag */
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#define PWR_CSR_SBF (1 << 1)
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/* WUF: Wakeup flag */
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#define PWR_CSR_WUF (1 << 0)
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/* --- PWR function prototypes ------------------------------------------- */
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BEGIN_DECLS
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void pwr_disable_backup_domain_write_protect(void);
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void pwr_enable_backup_domain_write_protect(void);
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void pwr_enable_power_voltage_detect(u32 pvd_level);
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void pwr_disable_power_voltage_detect(void);
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void pwr_clear_standby_flag(void);
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void pwr_clear_wakeup_flag(void);
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void pwr_set_standby_mode(void);
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void pwr_set_stop_mode(void);
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void pwr_voltage_regulator_on_in_stop(void);
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void pwr_voltage_regulator_low_power_in_stop(void);
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void pwr_enable_wakeup_pin(void);
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void pwr_disable_wakeup_pin(void);
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bool pwr_voltage_high(void);
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bool pwr_get_standby_flag(void);
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bool pwr_get_wakeup_flag(void);
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END_DECLS
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/**@}*/
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#endif
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