e5b3250382
Add the register definitions and some of the most basic helper functions for the new style BCD RTC module found on the F2, F4, L1, F3 and F0. This tries to keep as close to HACKING_COMMON_DOC as possible, while maintaining sane names.
157 lines
4.4 KiB
C
157 lines
4.4 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* The F1 RTC is a straight timestamp, a completely different peripheral to
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* that found in the F2, F3, F4, L1 and F0.
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*/
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#ifndef LIBOPENCM3_RTC_H
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#define LIBOPENCM3_RTC_H
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/stm32/pwr.h>
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#include <libopencm3/stm32/f1/rcc.h>
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/* --- RTC registers ------------------------------------------------------- */
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/* RTC control register high (RTC_CRH) */
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#define RTC_CRH MMIO32(RTC_BASE + 0x00)
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/* RTC control register low (RTC_CRL) */
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#define RTC_CRL MMIO32(RTC_BASE + 0x04)
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/* RTC prescaler load register (RTC_PRLH / RTC_PRLL) */
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#define RTC_PRLH MMIO32(RTC_BASE + 0x08)
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#define RTC_PRLL MMIO32(RTC_BASE + 0x0c)
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/* RTC prescaler divider register (RTC_DIVH / RTC_DIVL) */
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#define RTC_DIVH MMIO32(RTC_BASE + 0x10)
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#define RTC_DIVL MMIO32(RTC_BASE + 0x14)
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/* RTC counter register (RTC_CNTH / RTC_CNTL) */
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#define RTC_CNTH MMIO32(RTC_BASE + 0x18)
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#define RTC_CNTL MMIO32(RTC_BASE + 0x1c)
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/* RTC alarm register high (RTC_ALRH / RTC_ALRL) */
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#define RTC_ALRH MMIO32(RTC_BASE + 0x20)
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#define RTC_ALRL MMIO32(RTC_BASE + 0x24)
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/* --- RTC_CRH values -------------------------------------------------------*/
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/* Note: Bits [15:3] are reserved, and forced to 0 by hardware. */
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/* OWIE: Overflow interrupt enable */
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#define RTC_CRH_OWIE (1 << 2)
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/* ALRIE: Alarm interrupt enable */
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#define RTC_CRH_ALRIE (1 << 1)
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/* SECIE: Second interrupt enable */
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#define RTC_CRH_SECIE (1 << 0)
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/* --- RTC_CRL values -------------------------------------------------------*/
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/* Note: Bits [15:6] are reserved, and forced to 0 by hardware. */
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/* RTOFF: RTC operation OFF */
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#define RTC_CRL_RTOFF (1 << 5)
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/* CNF: Configuration flag */
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#define RTC_CRL_CNF (1 << 4)
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/* RSF: Registers synchronized flag */
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#define RTC_CRL_RSF (1 << 3)
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/* OWF: Overflow flag */
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#define RTC_CRL_OWF (1 << 2)
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/* ALRF: Alarm flag */
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#define RTC_CRL_ALRF (1 << 1)
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/* SECF: Second flag */
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#define RTC_CRL_SECF (1 << 0)
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/* --- RTC_PRLH values ------------------------------------------------------*/
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/* Note: Bits [15:4] are reserved, and forced to 0 by hardware. */
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/* TODO */
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/* --- RTC_PRLL values ------------------------------------------------------*/
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/* TODO */
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/* --- RTC_DIVH values ------------------------------------------------------*/
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/* Bits [15:4] are reserved. */
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/* TODO */
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/* --- RTC_DIVL values ------------------------------------------------------*/
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/* TODO */
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/* --- RTC_CNTH values ------------------------------------------------------*/
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/* TODO */
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/* --- RTC_CNTL values ------------------------------------------------------*/
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/* TODO */
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/* --- RTC_ALRH values ------------------------------------------------------*/
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/* TODO */
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/* --- RTC_ALRL values ------------------------------------------------------*/
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/* TODO */
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/* --- Function prototypes --------------------------------------------------*/
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typedef enum {
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RTC_SEC, RTC_ALR, RTC_OW,
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} rtcflag_t;
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BEGIN_DECLS
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void rtc_awake_from_off(osc_t clock_source);
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void rtc_enter_config_mode(void);
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void rtc_exit_config_mode(void);
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void rtc_set_alarm_time(u32 alarm_time);
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void rtc_enable_alarm(void);
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void rtc_disable_alarm(void);
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void rtc_set_prescale_val(u32 prescale_val);
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u32 rtc_get_counter_val(void);
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u32 rtc_get_prescale_div_val(void);
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u32 rtc_get_alarm_val(void);
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void rtc_set_counter_val(u32 counter_val);
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void rtc_interrupt_enable(rtcflag_t flag_val);
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void rtc_interrupt_disable(rtcflag_t flag_val);
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void rtc_clear_flag(rtcflag_t flag_val);
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u32 rtc_check_flag(rtcflag_t flag_val);
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void rtc_awake_from_standby(void);
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void rtc_auto_awake(osc_t clock_source, u32 prescale_val);
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END_DECLS
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#endif
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