c72f3d588a
All the macro arguments that are user supplied, or potentially, wrap properly in () as good practice. Probably missed one or two, and a lot of them are possibly unnecessary, but it's straightforward to just do it always. Fixes github issue #321
115 lines
3.6 KiB
C
115 lines
3.6 KiB
C
/** @addtogroup timer_defines
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@author @htmlonly © @endhtmlonly 2011 Fergus Noble <fergusnoble@gmail.com>
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA TIMER.H
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The order of header inclusion is important. timer.h includes the device
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specific memorymap.h header before including this header file.*/
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/** @cond */
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#ifdef LIBOPENCM3_TIMER_H
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/** @endcond */
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#ifndef LIBOPENCM3_TIMER_COMMON_F24_H
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#define LIBOPENCM3_TIMER_COMMON_F24_H
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#include <libopencm3/stm32/common/timer_common_all.h>
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/*
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* TIM2 and TIM5 are now 32bit and the following registers are now 32-bit wide:
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* CNT, ARR, CCR1, CCR2, CCR3, CCR4
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*/
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/* Timer 2/5 option register (TIMx_OR) */
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#define TIM_OR(tim_base) MMIO32((tim_base) + 0x50)
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#define TIM2_OR TIM_OR(TIM2)
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#define TIM5_OR TIM_OR(TIM5)
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/* --- TIM2_OR values ---------------------------------------------------- */
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/* ITR1_RMP */
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/****************************************************************************/
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/** @defgroup tim2_opt_trigger_remap TIM2_OR Timer 2 Option Register Internal
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Trigger 1 Remap
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Only available in F2 and F4 series.
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@ingroup timer_defines
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@{*/
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/** Internal Trigger 1 remapped to timer 8 trigger out */
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#define TIM2_OR_ITR1_RMP_TIM8_TRGOU (0x0 << 10)
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/** Internal Trigger 1 remapped to PTP trigger out */
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#define TIM2_OR_ITR1_RMP_PTP (0x1 << 10)
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/** Internal Trigger 1 remapped to USB OTG FS SOF */
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#define TIM2_OR_ITR1_RMP_OTG_FS_SOF (0x2 << 10)
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/** Internal Trigger 1 remapped to USB OTG HS SOF */
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#define TIM2_OR_ITR1_RMP_OTG_HS_SOF (0x3 << 10)
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/**@}*/
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#define TIM2_OR_ITR1_RMP_MASK (0x3 << 10)
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/* --- TIM5_OR values ---------------------------------------------------- */
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/* ITR4_RMP */
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/****************************************************************************/
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/** @defgroup tim5_opt_trigger_remap TIM5_OR Timer 5 Option Register Internal Trigger 4 Remap
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Only available in F2 and F4 series.
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@ingroup timer_defines
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@{*/
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/** Internal Trigger 4 remapped to GPIO (see reference manual) */
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#define TIM5_OR_TI4_RMP_GPIO (0x0 << 6)
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/** Internal Trigger 4 remapped to LSI internal clock */
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#define TIM5_OR_TI4_RMP_LSI (0x1 << 6)
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/** Internal Trigger 4 remapped to LSE internal clock */
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#define TIM5_OR_TI4_RMP_LSE (0x2 << 6)
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/** Internal Trigger 4 remapped to RTC output event */
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#define TIM5_OR_TI4_RMP_RTC (0x3 << 6)
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/**@}*/
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#define TIM5_OR_TI4_RMP_MASK (0x3 << 6)
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/** Input Capture input polarity */
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enum tim_ic_pol {
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TIM_IC_RISING,
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TIM_IC_FALLING,
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TIM_IC_BOTH,
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};
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/* --- Function prototypes ------------------------------------------------- */
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BEGIN_DECLS
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void timer_set_option(uint32_t timer_peripheral, uint32_t option);
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void timer_ic_set_polarity(uint32_t timer, enum tim_ic_id ic,
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enum tim_ic_pol pol);
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END_DECLS
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#endif
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/** @cond */
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#else
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#warning "timer_common_f24.h should not be included directly, only via timer.h"
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#endif
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/** @endcond */
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