709d98e0a8
the group defaults to the implicit container based on location, so drop all the explicit @ingroups, less to maintain. Properly use /**@}*/ to close all groups too, even though it mostly seems to have worked anyway. Properly close all groups opened for files.
203 lines
5.8 KiB
C
203 lines
5.8 KiB
C
/** @defgroup pwr_defines PWR Defines
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*
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* @brief <b>Defined Constants and Types for the STM32G0xx PWR Control</b>
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*
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* @ingroup STM32G0xx_defines
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*
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* @version 1.0.0
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_PWR_H
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#define LIBOPENCM3_PWR_H
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/**@{*/
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/** @defgroup pwr_registers PWR Registers
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@{*/
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/** Power control register 1 (PWR_CR1) */
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#define PWR_CR1 MMIO32(POWER_CONTROL_BASE + 0x00)
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/** Power control register 2 (PWR_CR2) */
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#define PWR_CR2 MMIO32(POWER_CONTROL_BASE + 0x04)
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/** Power control register 3 (PWR_CR3) */
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#define PWR_CR3 MMIO32(POWER_CONTROL_BASE + 0x08)
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/** Power control register 4 (PWR_CR4) */
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#define PWR_CR4 MMIO32(POWER_CONTROL_BASE + 0x0c)
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/** Power status register 1 (PWR_SR1) */
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#define PWR_SR1 MMIO32(POWER_CONTROL_BASE + 0x10)
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/** Power status registery 2 (PWR_SR2) */
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#define PWR_SR2 MMIO32(POWER_CONTROL_BASE + 0x14)
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/** Power status clear register (PWR_SCR) */
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#define PWR_SCR MMIO32(POWER_CONTROL_BASE + 0x18)
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#define PWR_PORT_A MMIO32(POWER_CONTROL_BASE + 0x20)
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#define PWR_PORT_B MMIO32(POWER_CONTROL_BASE + 0x28)
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#define PWR_PORT_C MMIO32(POWER_CONTROL_BASE + 0x30)
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#define PWR_PORT_D MMIO32(POWER_CONTROL_BASE + 0x38)
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#define PWR_PORT_E MMIO32(POWER_CONTROL_BASE + 0x40)
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#define PWR_PORT_F MMIO32(POWER_CONTROL_BASE + 0x48)
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#define PWR_PUCR(pwr_port) MMIO32((pwr_port) + 0x00)
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#define PWR_PDCR(pwr_port) MMIO32((pwr_port) + 0x04)
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/**@}*/
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/* --- PWR_CR1 values ------------------------------------------------------- */
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#define PWR_CR1_LPR (1 << 14)
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#define PWR_CR1_VOS_SHIFT 9
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#define PWR_CR1_VOS_MASK 0x3
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/** @defgroup pwr_cr1_vos VOS
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* @brief Voltage scaling range selection.
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@{*/
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#define PWR_CR1_VOS_RANGE_1 1
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#define PWR_CR1_VOS_RANGE_2 2
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/**@}*/
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#define PWR_CR1_DBP (1 << 8)
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#define PWR_CR1_FPD_LPSLP (1 << 5)
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#define PWR_CR1_FPD_LPRUN (1 << 4)
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#define PWR_CR1_FPD_STOP (1 << 3)
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#define PWR_CR1_LPMS_SHIFT 0
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#define PWR_CR1_LPMS_MASK 0x07
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/** @defgroup pwr_cr1_lpms LPMS
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* @ingroup STM32G0xx_pwr_defines
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* @brief Low-power mode selection
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@{*/
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#define PWR_CR1_LPMS_STOP_0 0
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#define PWR_CR1_LPMS_STOP_1 1
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#define PWR_CR1_LPMS_STANDBY 3
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#define PWR_CR1_LPMS_SHUTDOWN 4
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/**@}*/
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/* --- PWR_CR2 values ------------------------------------------------------- */
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#define PWR_CR2_PVDRT_SHIFT 4
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#define PWR_CR2_PVDRT_MASK 0x07
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/** @defgroup pwr_cr2_pvdrt PVDRT
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* @brief Power voltage detector rising threshold selection
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@{*/
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#define PWR_CR2_PVDRT_2V1 0x00
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#define PWR_CR2_PVDRT_2V2 0x01
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#define PWR_CR2_PVDRT_2V5 0x02
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#define PWR_CR2_PVDRT_2V6 0x03
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#define PWR_CR2_PVDRT_2V7 0x04
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#define PWR_CR2_PVDRT_2V9 0x05
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#define PWR_CR2_PVDRT_3V0 0x06
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#define PWR_CR2_PVDRT_PVD_IN 0x07
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/**@}*/
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#define PWR_CR2_PVDFT_SHIFT 1
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#define PWR_CR2_PVDFT_MASK 0x07
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/** @defgroup pwr_cr2_pvdft PVDFT
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* @brief Power voltage detector falling threshold selection
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@{*/
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#define PWR_CR2_PVDFT_2V0 0x00
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#define PWR_CR2_PVDFT_2V2 0x01
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#define PWR_CR2_PVDFT_2V4 0x02
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#define PWR_CR2_PVDFT_2V5 0x03
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#define PWR_CR2_PVDFT_2V6 0x04
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#define PWR_CR2_PVDFT_2V8 0x05
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#define PWR_CR2_PVDFT_2V9 0x06
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/**@}*/
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#define PWR_CR2_PVDE (1 << 0)
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/* --- PWR_CR3 values ------------------------------------------------------- */
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#define PWR_CR3_EIWUL (1 << 15)
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#define PWR_CR3_APC (1 << 10)
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#define PWR_CR3_ULPEN (1 << 9)
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#define PWR_CR3_RRS (1 << 8)
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#define PWR_CR3_EWUP6 (1 << 5)
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#define PWR_CR3_EWUP5 (1 << 4)
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#define PWR_CR3_EWUP4 (1 << 3)
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#define PWR_CR3_EWUP2 (1 << 1)
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#define PWR_CR3_EWUP1 (1 << 0)
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/* --- PWR_CR4 values ------------------------------------------------------- */
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#define PWR_CR4_VBRS (1 << 9)
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#define PWR_CR4_VBE (1 << 8)
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#define PWR_CR4_WP6 (1 << 5)
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#define PWR_CR4_WP5 (1 << 4)
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#define PWR_CR4_WP4 (1 << 3)
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#define PWR_CR4_WP2 (1 << 1)
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#define PWR_CR4_WP1 (1 << 0)
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/* --- PWR_SR1 values ------------------------------------------------------- */
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#define PWR_SR1_WUFI (1 << 15)
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#define PWR_SR1_SBF (1 << 8)
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#define PWR_SR1_WUF6 (1 << 5)
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#define PWR_SR1_WUF5 (1 << 4)
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#define PWR_SR1_WUF4 (1 << 3)
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#define PWR_SR1_WUF2 (1 << 1)
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#define PWR_SR1_WUF1 (1 << 0)
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/* --- PWR_SR2 values ------------------------------------------------------- */
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#define PWR_SR2_PVDO (1 << 11)
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#define PWR_SR2_VOSF (1 << 10)
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#define PWR_SR2_REGLPF (1 << 9)
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#define PWR_SR2_REGLPS (1 << 8)
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#define PWR_SR2_FLASHRDY (1 << 8)
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/* --- PWR_SCR values ------------------------------------------------------- */
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#define PWR_SCR_CSBF (1 << 8)
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#define PWR_SCR_CWUF6 (1 << 5)
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#define PWR_SCR_CWUF5 (1 << 4)
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#define PWR_SCR_CWUF4 (1 << 3)
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#define PWR_SCR_CWUF2 (1 << 1)
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#define PWR_SCR_CWUF1 (1 << 0)
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/* --- Function prototypes ------------------------------------------------- */
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enum pwr_vos_scale {
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PWR_SCALE1 = PWR_CR1_VOS_RANGE_1,
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PWR_SCALE2 = PWR_CR1_VOS_RANGE_2,
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};
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BEGIN_DECLS
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void pwr_set_vos_scale(enum pwr_vos_scale scale);
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void pwr_disable_backup_domain_write_protect(void);
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void pwr_enable_backup_domain_write_protect(void);
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void pwr_set_low_power_mode_selection(uint32_t lpms);
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void pwr_enable_power_voltage_detect(uint32_t pvdr_level, uint32_t pvdf_level);
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void pwr_disable_power_voltage_detect(void);
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END_DECLS
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/**@}*/
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#endif
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