103 lines
3.3 KiB
C
103 lines
3.3 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/lpc43xx/gpio.h>
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#include <libopencm3/lpc43xx/scu.h>
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#include <libopencm3/lpc43xx/cgu.h>
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#include <libopencm3/lpc43xx/i2c.h>
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//FIXME generalize and move to drivers
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#define SCU_SFSI2C0_SCL_EFP (1 << 1) /* 3 ns glitch filter */
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#define SCU_SFSI2C0_SCL_EHD (1 << 2) /* Fast-mode Plus transmit */
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#define SCU_SFSI2C0_SCL_EZI (1 << 3) /* Enable the input receiver */
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#define SCU_SFSI2C0_SCL_ZIF (1 << 7) /* Disable input glitch filter */
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#define SCU_SFSI2C0_SDA_EFP (1 << 8) /* 3 ns glitch filter */
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#define SCU_SFSI2C0_SDA_EHD (1 << 10) /* Fast-mode Plus transmit */
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#define SCU_SFSI2C0_SDA_EZI (1 << 11) /* Enable the input receiver */
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#define SCU_SFSI2C0_SDA_ZIF (1 << 15) /* Disable input glitch filter */
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#define I2C_CONCLR_AAC (1 << 2) /* Assert acknowledge Clear */
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#define I2C_CONCLR_SIC (1 << 3) /* I2C interrupt Clear */
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#define I2C_CONCLR_STAC (1 << 5) /* START flag Clear */
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#define I2C_CONCLR_I2ENC (1 << 6) /* I2C interface Disable bit */
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#define I2C_CONSET_AA (1 << 2) /* Assert acknowledge flag */
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#define I2C_CONSET_SI (1 << 3) /* I2C interrupt flag */
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#define I2C_CONSET_STO (1 << 4) /* STOP flag */
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#define I2C_CONSET_STA (1 << 5) /* START flag */
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#define I2C_CONSET_I2EN (1 << 6) /* I2C interface enable */
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#define CGU_SRC_32K 0x00
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#define CGU_SRC_IRC 0x01
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#define CGU_SRC_ENET_RX 0x02
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#define CGU_SRC_ENET_TX 0x03
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#define CGU_SRC_GP_CLKIN 0x04
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#define CGU_SRC_XTAL 0x06
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#define CGU_SRC_PLL0USB 0x07
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#define CGU_SRC_PLL0AUDIO 0x08
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#define CGU_SRC_PLL1 0x09
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#define CGU_SRC_IDIVA 0x0C
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#define CGU_SRC_IDIVB 0x0D
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#define CGU_SRC_IDIVC 0x0E
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#define CGU_SRC_IDIVD 0x0F
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#define CGU_SRC_IDIVE 0x10
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#define CGU_BASE_CLK_PD (1 << 0) /* output stage power-down */
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#define CGU_BASE_CLK_AUTOBLOCK (1 << 11) /* block clock automatically */
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#define CGU_BASE_CLK_SEL_SHIFT 24 /* clock source selection (5 bits) */
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void i2c0_init()
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{
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/* enable input on SCL and SDA pins */
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SCU_SFSI2C0 = (SCU_SFSI2C0_SCL_EZI | SCU_SFSI2C0_SDA_EZI);
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/* use PLL1 as clock source for APB1 (including I2C0) */
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CGU_BASE_APB1_CLK = (CGU_SRC_PLL1 << CGU_BASE_CLK_SEL_SHIFT);
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//FIXME assuming we're on IRC at 96 MHz
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/* 400 kHz I2C */
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I2C0_SCLH = 120;
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I2C0_SCLL = 120;
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/* 100 kHz I2C */
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//I2C0_SCLH = 480;
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//I2C0_SCLL = 480;
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/* clear the control bits */
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I2C0_CONCLR = (I2C_CONCLR_AAC | I2C_CONCLR_SIC
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| I2C_CONCLR_STAC | I2C_CONCLR_I2ENC);
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/* enable I2C0 */
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I2C0_CONSET = I2C_CONSET_I2EN;
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}
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int main(void)
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{
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int i;
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i2c0_init();
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//TODO I2C tx/rx
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return 0;
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}
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