140 lines
5.8 KiB
C
140 lines
5.8 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Gareth McMullin <gareth@blacksphere.co.nz>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_OTG_FS_H
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#define LIBOPENCM3_OTG_FS_H
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/common.h>
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/* Core Global Control and Status Registers */
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#define OTG_FS_OTGCTL MMIO32(USB_OTG_FS_BASE + 0x000)
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#define OTG_FS_GOTGINT MMIO32(USB_OTG_FS_BASE + 0x004)
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#define OTG_FS_GAHBCFG MMIO32(USB_OTG_FS_BASE + 0x008)
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#define OTG_FS_GUSBCFG MMIO32(USB_OTG_FS_BASE + 0x00C)
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#define OTG_FS_GRSTCTL MMIO32(USB_OTG_FS_BASE + 0x010)
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#define OTG_FS_GINTSTS MMIO32(USB_OTG_FS_BASE + 0x014)
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#define OTG_FS_GINTMSK MMIO32(USB_OTG_FS_BASE + 0x018)
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#define OTG_FS_GRXSTSR MMIO32(USB_OTG_FS_BASE + 0x01C)
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#define OTG_FS_GRXSTSP MMIO32(USB_OTG_FS_BASE + 0x020)
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#define OTG_FS_GRXFSIZ MMIO32(USB_OTG_FS_BASE + 0x024)
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#define OTG_FS_GNPTXFSIZ MMIO32(USB_OTG_FS_BASE + 0x028)
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#define OTG_FS_GNPTXSTS MMIO32(USB_OTG_FS_BASE + 0x02C)
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#define OTG_FS_GCCFG MMIO32(USB_OTG_FS_BASE + 0x038)
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#define OTG_FS_CID MMIO32(USB_OTG_FS_BASE + 0x03C)
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#define OTG_FS_HPTXFSIZ MMIO32(USB_OTG_FS_BASE + 0x100)
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#define OTG_FS_DIEPTXF(x) MMIO32(USB_OTG_FS_BASE + 0x104 + 4*(x))
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/* Host-mode Control and Status Registers */
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#define OTG_FS_HCFG MMIO32(USB_OTG_FS_BASE + 0x400)
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#define OTG_FS_HFIR MMIO32(USB_OTG_FS_BASE + 0x404)
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#define OTG_FS_HFNUM MMIO32(USB_OTG_FS_BASE + 0x408)
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#define OTG_FS_HPTXSTS MMIO32(USB_OTG_FS_BASE + 0x410)
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#define OTG_FS_HAINT MMIO32(USB_OTG_FS_BASE + 0x414)
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#define OTG_FS_HAINTMSK MMIO32(USB_OTG_FS_BASE + 0x418)
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#define OTG_FS_HPRT MMIO32(USB_OTG_FS_BASE + 0x440)
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#define OTG_FS_HCCHARx MMIO32(USB_OTG_FS_BASE + 0x500)
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#define OTG_FS_HCINTx MMIO32(USB_OTG_FS_BASE + 0x508)
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#define OTG_FS_HCINTMSKx MMIO32(USB_OTG_FS_BASE + 0x50C)
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#define OTG_FS_HCTSIZx MMIO32(USB_OTG_FS_BASE + 0x510)
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/* Device-mode Control and Status Registers */
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#define OTG_FS_DCFG MMIO32(USB_OTG_FS_BASE + 0x800)
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#define OTG_FS_DCTL MMIO32(USB_OTG_FS_BASE + 0x804)
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#define OTG_FS_DSTS MMIO32(USB_OTG_FS_BASE + 0x808)
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#define OTG_FS_DIEPMSK MMIO32(USB_OTG_FS_BASE + 0x810)
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#define OTG_FS_DOEPMSK MMIO32(USB_OTG_FS_BASE + 0x814)
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#define OTG_FS_DAINT MMIO32(USB_OTG_FS_BASE + 0x818)
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#define OTG_FS_DAINTMSK MMIO32(USB_OTG_FS_BASE + 0x81C)
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#define OTG_FS_DVBUSDIS MMIO32(USB_OTG_FS_BASE + 0x828)
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#define OTG_FS_DVBUSPULSE MMIO32(USB_OTG_FS_BASE + 0x82C)
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#define OTG_FS_DIEPEMPMSK MMIO32(USB_OTG_FS_BASE + 0x834)
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#define OTG_FS_DIEPCTL0 MMIO32(USB_OTG_FS_BASE + 0x900)
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#define OTG_FS_DIEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0x900 + 0x20*(x))
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#define OTG_FS_DOEPCTL0 MMIO32(USB_OTG_FS_BASE + 0xB00)
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#define OTG_FS_DOEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0xB00 + 0x20*(x))
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#define OTG_FS_DIEPINT(x) MMIO32(USB_OTG_FS_BASE + 0x908 + 0x20*(x))
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#define OTG_FS_DOEPINT(x) MMIO32(USB_OTG_FS_BASE + 0xB08 + 0x20*(x))
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#define OTG_FS_DIEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0x910)
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#define OTG_FS_DOEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0xB10)
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#define OTG_FS_DIEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0x910 + 0x20*(x))
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#define OTG_FS_DTXFSTS(x) MMIO32(USB_OTG_FS_BASE + 0x918 + 0x20*(x))
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#define OTG_FS_DOEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0xB10 + 0x20*(x))
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/* Power and clock gating control and status register */
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#define OTH_FS_PCGCR MMIO32(USB_OTG_FS_BASE + 0xE00)
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/* Global CSRs */
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/* OTG_FS AHB configuration register (OTG_FS_GAHBCFG) */
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#define OTG_FS_GAHBCFG_GINT 0x0001
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#define OTG_FS_GAHBCFG_TXFELVL 0x0080
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#define OTG_FS_GAHBCFG_PTXFELVL 0x0100
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/* OTG_FS USB configuration register (OTG_FS_GUSBCFG) */
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#define OTG_FS_GUSBCFG_TOCAL 0x00000003
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#define OTG_FS_GUSBCFG_SRPCAP 0x00000100
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#define OTG_FS_GUSBCFG_HNPCAP 0x00000200
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#define OTG_FS_GUSBCFG_TRDT 0x00003C00
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#define OTG_FS_GUSBCFG_NPTXRWEN 0x00004000
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#define OTG_FS_GUSBCFG_FHMOD 0x20000000
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#define OTG_FS_GUSBCFG_FDMOD 0x40000000
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#define OTG_FS_GUSBCFG_CTXPKT 0x80000000
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/* OTG_FS interrupt mask register (OTG_FS_GINTMSK) */
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#define OTG_FS_GINTMSK_MMISM 0x00000002
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#define OTG_FS_GINTMSK_OTGINT 0x00000004
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#define OTG_FS_GINTMSK_SOFM 0x00000008
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#define OTG_FS_GINTMSK_RXFLVLM 0x00000010
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#define OTG_FS_GINTMSK_NPTXFEM 0x00000020
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#define OTG_FS_GINTMSK_GINAKEFFM 0x00000040
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#define OTG_FS_GINTMSK_GONAKEFFM 0x00000080
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#define OTG_FS_GINTMSK_ESUSPM 0x00000400
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#define OTG_FS_GINTMSK_USBSUSPM 0x00000800
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#define OTG_FS_GINTMSK_USBRST 0x00001000
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#define OTG_FS_GINTMSK_ENUMDNEM 0x00002000
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#define OTG_FS_GINTMSK_ISOODRPM 0x00004000
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#define OTG_FS_GINTMSK_EOPFM 0x00008000
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#define OTG_FS_GINTMSK_EPMISM 0x00020000
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#define OTG_FS_GINTMSK_IEPINT 0x00040000
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#define OTG_FS_GINTMSK_OEPINT 0x00080000
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#define OTG_FS_GINTMSK_IISOIXFRM 0x00100000
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#define OTG_FS_GINTMSK_IISOOXFRM 0x00200000
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#define OTG_FS_GINTMSK_IPXFRM 0x00200000
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#define OTG_FS_GINTMSK_PRTIM 0x01000000
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#define OTG_FS_GINTMSK_HCIM 0x02000000
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#define OTG_FS_GINTMSK_PTXFEM 0x04000000
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#define OTG_FS_GINTMSK_CIDSCHGM 0x10000000
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#define OTG_FS_GINTMSK_DISCINT 0x20000000
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#define OTG_FS_GINTMSK_SRQIM 0x40000000
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#define OTG_FS_GINTMSK_WUIM 0x80000000
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/* Device-mode CSRs */
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/* OTG_FS device configuration register (OTG_FS_DCFG) */
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#define OTG_FS_DCFG_DSPD 0x0003
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#define OTG_FS_DCFG_NZLSOHSK 0x0004
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#define OTG_FS_DCFG_DAD 0x07F0
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#define OTG_FS_DCFG_PFIVL 0x1800
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#endif
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