eafc46ff24
This then eliminates the misguided attempts at merging f2/4 and f3 flash support. Some headers remain.
180 lines
6.0 KiB
C
180 lines
6.0 KiB
C
#ifndef LIBOPENCM3_FLASH_H
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#define LIBOPENCM3_FLASH_H
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/** @addtogroup flash_defines
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*
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* @author @htmlonly © @endhtmlonly 2017
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* Matthew Lai <m@matthewlai.ca>
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* @author @htmlonly © @endhtmlonly 2010
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* Thomas Otto <tommi@viadmin.org>
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* @author @htmlonly © @endhtmlonly 2010
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* Mark Butler <mbutler@physics.otago.ac.nz>
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*
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2017 Matthew Lai <m@matthewlai.ca>
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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* Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/stm32/common/flash_common_all.h>
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#include <libopencm3/stm32/common/flash_common_f.h>
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/*
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* For details see:
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* PM0081 Programming manual: STM32F40xxx and STM32F41xxx Flash programming
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* September 2011, Doc ID 018520 Rev 1
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* https://github.com/libopencm3/libopencm3-archive/blob/master/st_micro/DM00023388.pdf
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*/
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/*
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* Differences between F7 and F4:
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* 1. icache and dcache are now combined into a unified ART cache. The CPU has
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* its own d/i-caches, but those are unrelated to this. They are on the
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* AXIM bus.
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* 2. There's an OPTCR1 is now used for boot addresses. Write protect bits
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* are in OPTCR. Why does F4 have 2 copies of nWRP?
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* 3. Latency field in FLASH_ACR is now 4 bits. Some CPU frequencies supported
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* by F7 require more than 7 wait states.
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* 4. FLASH_SR_PGSERR (programming sequence error) is now FLASH_SR_ERSERR (
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* erase sequence error).
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* 6. There are now two watchdogs - IWDG (independent watchdog) and WWDG (
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* window watchdog).
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*/
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/**@{*/
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/* --- FLASH registers ----------------------------------------------------- */
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#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00)
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#define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04)
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#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08)
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#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C)
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#define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10)
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#define FLASH_OPTCR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14)
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#define FLASH_OPTCR1 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18)
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/* --- FLASH Keys -----------------------------------------------------------*/
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#define FLASH_KEYR_KEY1 0x45670123UL
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#define FLASH_KEYR_KEY2 0xcdef89abUL
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#define FLASH_OPTKEYR_KEY1 0x08192a3bUL
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#define FLASH_OPTKEYR_KEY2 0x4c5d6e7fUL
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/* --- FLASH_ACR values ---------------------------------------------------- */
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#define FLASH_ACR_ARTRST (1 << 11)
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#define FLASH_ACR_ARTEN (1 << 9)
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#define FLASH_ACR_PRFTEN (1 << 8)
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#define FLASH_ACR_LATENCY_SHIFT 0
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#define FLASH_ACR_LATENCY_MASK 0x0f
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/* --- FLASH_SR values ----------------------------------------------------- */
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#define FLASH_SR_BSY (1 << 16)
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#define FLASH_SR_ERSERR (1 << 7)
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#define FLASH_SR_PGPERR (1 << 6)
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#define FLASH_SR_PGAERR (1 << 5)
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#define FLASH_SR_WRPERR (1 << 4)
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#define FLASH_SR_OPERR (1 << 1)
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#define FLASH_SR_EOP (1 << 0)
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/* --- FLASH_CR values ----------------------------------------------------- */
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#define FLASH_CR_LOCK (1 << 31)
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#define FLASH_CR_ERRIE (1 << 25)
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#define FLASH_CR_EOPIE (1 << 24)
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#define FLASH_CR_STRT (1 << 16)
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#define FLASH_CR_PROGRAM_MASK 0x3
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#define FLASH_CR_PROGRAM_SHIFT 8
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/** @defgroup flash_cr_program_width Flash programming width
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@ingroup flash_group
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@{*/
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#define FLASH_CR_PROGRAM_X8 0
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#define FLASH_CR_PROGRAM_X16 1
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#define FLASH_CR_PROGRAM_X32 2
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#define FLASH_CR_PROGRAM_X64 3
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/**@}*/
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#define FLASH_CR_SNB_SHIFT 3
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#define FLASH_CR_SNB_MASK 0x1f
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#define FLASH_CR_MER (1 << 2)
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#define FLASH_CR_SER (1 << 1)
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#define FLASH_CR_PG (1 << 0)
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/* --- FLASH_OPTCR values -------------------------------------------------- */
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#define FLASH_OPTCR_IWDG_STOP (1 << 31)
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#define FLASH_OPTCR_IWDG_STDBY (1 << 30)
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#define FLASH_OPTCR_NWRP_SHIFT 16
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#define FLASH_OPTCR_NWRP_MASK 0xff
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#define FLASH_OPTCR_RDP_SHIFT 8
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#define FLASH_OPTCR_RDP_MASK 0xff
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#define FLASH_OPTCR_NRST_STDBY (1 << 7)
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#define FLASH_OPTCR_NRST_STOP (1 << 6)
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#define FLASH_OPTCR_IWDG_SW (1 << 5)
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#define FLASH_OPTCR_WWDG_SW (1 << 4)
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#define FLASH_OPTCR_BOR_LEV_MASK 3
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#define FLASH_OPTCR_BOR_LEV_SHIFT 2
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#define FLASH_OPTCR_BOR_LEV_3 0x00
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#define FLASH_OPTCR_BOR_LEV_2 0x01
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#define FLASH_OPTCR_BOR_LEV_1 0x02
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#define FLASH_OPTCR_BOR_OFF 0x03
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#define FLASH_OPTCR_OPTSTRT (1 << 1)
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#define FLASH_OPTCR_OPTLOCK (1 << 0)
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/* --- FLASH_OPTCR1 values ------------------------------------------------- */
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#define FLASH_OPTCR1_BOOT_ADD1_MASK 0xffff
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#define FLASH_OPTCR1_BOOT_ADD1_SHIFT 16
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#define FLASH_OPTCR1_BOOT_ADD0_MASK 0xffff
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#define FLASH_OPTCR1_BOOT_ADD0_SHIFT 0
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/* --- Function prototypes ------------------------------------------------- */
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BEGIN_DECLS
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void flash_clear_pgperr_flag(void);
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void flash_lock_option_bytes(void);
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void flash_clear_erserr_flag(void);
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void flash_clear_wrperr_flag(void);
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void flash_clear_pgaerr_flag(void);
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void flash_art_enable(void);
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void flash_art_disable(void);
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void flash_art_reset(void);
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void flash_erase_all_sectors(uint32_t program_size);
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void flash_erase_sector(uint8_t sector, uint32_t program_size);
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void flash_program_double_word(uint32_t address, uint64_t data);
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void flash_program_word(uint32_t address, uint32_t data);
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void flash_program_half_word(uint32_t address, uint16_t data);
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void flash_program_byte(uint32_t address, uint8_t data);
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void flash_program(uint32_t address, uint8_t *data, uint32_t len);
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void flash_program_option_bytes(uint32_t data);
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END_DECLS
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/**@}*/
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#endif
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