330d5fd5be
GD32F1X0 (X can be 3, 5, 7 and 9) is a series of Cortex-M3 MCUs by GigaDevice, which features pin-to-pin package compatibility with STM32F030 MCU line. F150 adds USB support to F130, and F170/F190 adds CAN support. Currently the code mainly targets GD32F130 and F150 chips. Some register are different between F130/150 and F170/190, just like the difference between STM32F1 Performance line and Connectivity line. From the perspective of registers and memory map, GD32F1X0 seems like a mixture between STM32F1 and STM32F0 (because it is designed to be pin-to-pin compatible with F0, but with Cortex-M3 like F1). A bunch of code are shared between STM32 and GD32, and these code are specially processed to include the GD32 headers instead of STM32 headers when meet GD32F1X0. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Karl Palsson <karlp@tweak.net.au> gd32/rcc.[ch] are forks of stm32f1/rcc gd32/flash.[ch] are forks of stm32f0/flash No attempts at deduplicating this have been done at this stage. We can see where they move in the future.
110 lines
3.9 KiB
C
110 lines
3.9 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2019 Iceonwy Zheng <icenowy@aosc.io>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_MEMORYMAP_H
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#define LIBOPENCM3_MEMORYMAP_H
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#include <libopencm3/cm3/memorymap.h>
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/* --- GD32 specific peripheral definitions ------------------------------- */
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/* Memory map for all buses */
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#define FLASH_BASE (0x08000000U)
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#define PERIPH_BASE (0x40000000U)
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#define INFO_BASE (0x1ffff000U)
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#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)
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#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)
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#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)
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#define PERIPH_BASE_AHB2 (PERIPH_BASE + 0x8000000)
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/* Register boundary addresses */
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/* APB1 */
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#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)
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#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)
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#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)
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#define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000)
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/* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */
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#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800)
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#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)
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#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)
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/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */
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#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)
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/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */
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#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
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#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)
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#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)
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#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00)
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#define USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6000)
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#define USB_SRAM_BASE (PERIPH_BASE_APB1 + 0x6000)
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#define BACKUP_REGS_BASE (RTC_BASE + 0x50)
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#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)
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#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400)
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#define CEC_BASE (PERIPH_BASE_APB1 + 0x7800)
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/* PERIPH_BASE_APB1 + 0x7c00 (0x4000 7c00 - 0x4000 FFFF): Reserved */
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/* APB2 */
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#define SYSCFG_COMP_BASE (PERIPH_BASE_APB2 + 0x0000)
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#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)
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#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2400)
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#define TIM1_BASE (PERIPH_BASE_APB2 + 0x2c00)
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#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)
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#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800)
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#define TIM15_BASE (PERIPH_BASE_APB2 + 0x4000)
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#define TIM16_BASE (PERIPH_BASE_APB2 + 0x4400)
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#define TIM17_BASE (PERIPH_BASE_APB2 + 0x4800)
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/* PERIPH_BASE_APB2 + 0x5800 (0x4001 5800 - 0x4001 7FFF): Reserved */
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/* AHB1 */
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#define DMA1_BASE (PERIPH_BASE_AHB1 + 0x00000)
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#define RCC_BASE (PERIPH_BASE_AHB1 + 0x01000)
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#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x02000)
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#define CRC_BASE (PERIPH_BASE_AHB1 + 0x03000)
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#define TSC_BASE (PERIPH_BASE_AHB1 + 0x03000)
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/* AHB 2 */
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#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000)
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#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400)
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#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800)
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#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0c00)
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#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400)
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/* Device Electronic Signature */
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#define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x7e0)
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#define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7ac)
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/* Ignore the "reserved for future use" half of the first word */
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#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)
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#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)
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#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8)
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#endif
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