330d5fd5be
GD32F1X0 (X can be 3, 5, 7 and 9) is a series of Cortex-M3 MCUs by GigaDevice, which features pin-to-pin package compatibility with STM32F030 MCU line. F150 adds USB support to F130, and F170/F190 adds CAN support. Currently the code mainly targets GD32F130 and F150 chips. Some register are different between F130/150 and F170/190, just like the difference between STM32F1 Performance line and Connectivity line. From the perspective of registers and memory map, GD32F1X0 seems like a mixture between STM32F1 and STM32F0 (because it is designed to be pin-to-pin compatible with F0, but with Cortex-M3 like F1). A bunch of code are shared between STM32 and GD32, and these code are specially processed to include the GD32 headers instead of STM32 headers when meet GD32F1X0. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Karl Palsson <karlp@tweak.net.au> gd32/rcc.[ch] are forks of stm32f1/rcc gd32/flash.[ch] are forks of stm32f0/flash No attempts at deduplicating this have been done at this stage. We can see where they move in the future.
527 lines
17 KiB
C
527 lines
17 KiB
C
/** @defgroup rcc_defines RCC Defines
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*
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* @brief <b>Defined Constants and Types for the GD32F1x0 Reset and Clock
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* Control</b>
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*
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* @ingroup GD32F1x0_defines
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*
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* @version 1.0.0
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*
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* @author @htmlonly © @endhtmlonly 2009
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* Federico Ruiz-Ugalde \<memeruiz at gmail dot com\>
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* @author @htmlonly © @endhtmlonly 2009
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* Uwe Hermann <uwe@hermann-uwe.de>
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*
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* @date 18 August 2012
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*
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* LGPL License Terms @ref lgpl_license
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* */
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io>
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#ifndef LIBOPENCM3_RCC_H
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#define LIBOPENCM3_RCC_H
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/* --- RCC registers ------------------------------------------------------- */
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#define RCC_CR MMIO32(RCC_BASE + 0x00)
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#define RCC_CFGR MMIO32(RCC_BASE + 0x04)
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#define RCC_CIR MMIO32(RCC_BASE + 0x08)
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#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x0c)
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#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x10)
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#define RCC_AHBENR MMIO32(RCC_BASE + 0x14)
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#define RCC_APB2ENR MMIO32(RCC_BASE + 0x18)
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#define RCC_APB1ENR MMIO32(RCC_BASE + 0x1c)
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#define RCC_BDCR MMIO32(RCC_BASE + 0x20)
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#define RCC_CSR MMIO32(RCC_BASE + 0x24)
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#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28)
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#define RCC_CFGR2 MMIO32(RCC_BASE + 0x2c)
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#define RCC_CFGR3 MMIO32(RCC_BASE + 0x30)
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#define RCC_CR2 MMIO32(RCC_BASE + 0x34)
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/* --- RCC_CR values ------------------------------------------------------- */
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#define RCC_CR_PLLRDY (1 << 25)
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#define RCC_CR_PLLON (1 << 24)
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#define RCC_CR_CSSON (1 << 19)
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#define RCC_CR_HSEBYP (1 << 18)
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#define RCC_CR_HSERDY (1 << 17)
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#define RCC_CR_HSEON (1 << 16)
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/* HSICAL: [15:8] */
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/* HSITRIM: [7:3] */
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#define RCC_CR_HSIRDY (1 << 1)
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#define RCC_CR_HSION (1 << 0)
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/* --- RCC_CFGR values ----------------------------------------------------- */
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#define RCC_CFGR_PLLNODIV (1 << 31)
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#define RCC_CFGR_MCOPRE_SHIFT 28
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#define RCC_CFGR_MCOPRE (7 << RCC_CFGR_MCOPRE_SHIFT)
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#define RCC_CFGR_MCOPRE_DIV1 (0 << RCC_CFGR_MCOPRE_SHIFT)
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#define RCC_CFGR_MCOPRE_DIV2 (1 << RCC_CFGR_MCOPRE_SHIFT)
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#define RCC_CFGR_MCOPRE_DIV4 (2 << RCC_CFGR_MCOPRE_SHIFT)
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#define RCC_CFGR_MCOPRE_DIV8 (3 << RCC_CFGR_MCOPRE_SHIFT)
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#define RCC_CFGR_MCOPRE_DIV16 (4 << RCC_CFGR_MCOPRE_SHIFT)
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#define RCC_CFGR_MCOPRE_DIV32 (5 << RCC_CFGR_MCOPRE_SHIFT)
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#define RCC_CFGR_MCOPRE_DIV64 (6 << RCC_CFGR_MCOPRE_SHIFT)
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#define RCC_CFGR_MCOPRE_DIV128 (7 << RCC_CFGR_MCOPRE_SHIFT)
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#define RCC_CFGR_PLLMUL_4_SHIFT 27
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#define RCC_CFGR_PLLMUL_4 (1 << RCC_CFGR_PLLMUL_4_SHIFT)
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#define RCC_CFGR_MCO_SHIFT 24
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#define RCC_CFGR_MCO_MASK 0x7
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#define RCC_CFGR_MCO_NOCLK 0
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#define RCC_CFGR_MCO_HSI14 1
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#define RCC_CFGR_MCO_LSI 2
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#define RCC_CFGR_MCO_LSE 3
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#define RCC_CFGR_MCO_SYSCLK 4
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#define RCC_CFGR_MCO_HSI 5
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#define RCC_CFGR_MCO_HSE 6
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#define RCC_CFGR_MCO_PLL 7
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#define RCC_CFGR_USBPRE_SHIFT 22
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#define RCC_CFGR_USBPRE (3 << RCC_CFGR_USBPRE_SHIFT)
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#define RCC_CFGR_PLLMUL_0_3_SHIFT 18
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#define RCC_CFGR_PLLMUL_0_3 (0xF << RCC_CFGR_PLLMUL_0_3_SHIFT)
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#define RCC_CFGR_PLLXTPRE (1 << 17)
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#define RCC_CFGR_PLLSRC (1 << 16)
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#define RCC_CFGR_ADCPRE_SHIFT 14
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#define RCC_CFGR_ADCPRE (3 << RCC_CFGR_ADCPRE_SHIFT)
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#define RCC_CFGR_PPRE2_SHIFT 11
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#define RCC_CFGR_PPRE2 (7 << RCC_CFGR_PPRE2_SHIFT)
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#define RCC_CFGR_PPRE1_SHIFT 8
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#define RCC_CFGR_PPRE1 (7 << RCC_CFGR_PPRE1_SHIFT)
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#define RCC_CFGR_HPRE_SHIFT 4
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#define RCC_CFGR_HPRE (0xF << RCC_CFGR_HPRE_SHIFT)
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#define RCC_CFGR_SWS_SHIFT 2
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#define RCC_CFGR_SWS (3 << RCC_CFGR_SWS_SHIFT)
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#define RCC_CFGR_SW_SHIFT 0
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#define RCC_CFGR_SW (3 << RCC_CFGR_SW_SHIFT)
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/* USBPRE: USB prescaler (RCC_CFGR[23:22]) */
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#define RCC_CFGR_USBPRE_PLL_CLK_DIV1_5 0x0
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#define RCC_CFGR_USBPRE_PLL_CLK_NODIV 0x1
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#define RCC_CFGR_USBPRE_PLL_CLK_DIV2_5 0x2
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#define RCC_CFGR_USBPRE_PLL_CLK_DIV2 0x3
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/* PLLMUL: PLL multiplication factor */
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#define RCC_CFGR_PLLMUL_PLL_CLK_MUL2 0x0
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#define RCC_CFGR_PLLMUL_PLL_CLK_MUL3 0x1
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#define RCC_CFGR_PLLMUL_PLL_CLK_MUL4 0x2
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#define RCC_CFGR_PLLMUL_PLL_CLK_MUL5 0x3
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#define RCC_CFGR_PLLMUL_PLL_CLK_MUL6 0x4
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#define RCC_CFGR_PLLMUL_PLL_CLK_MUL7 0x5
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#define RCC_CFGR_PLLMUL_PLL_CLK_MUL8 0x6
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#define RCC_CFGR_PLLMUL_PLL_CLK_MUL9 0x7
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#define RCC_CFGR_PLLMUL_PLL_CLK_MUL10 0x8
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#define RCC_CFGR_PLLMUL_PLL_CLK_MUL11 0x9
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#define RCC_CFGR_PLLMUL_PLL_CLK_MUL12 0xa
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#define RCC_CFGR_PLLMUL_PLL_CLK_MUL13 0xb
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#define RCC_CFGR_PLLMUL_PLL_CLK_MUL14 0xc
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#define RCC_CFGR_PLLMUL_PLL_CLK_MUL15 0xd
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#define RCC_CFGR_PLLMUL_PLL_CLK_MUL16 0xe
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/* PLLXTPRE: HSE divider for PLL entry */
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#define RCC_CFGR_PLLXTPRE_HSE_CLK 0x0
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#define RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2 0x1
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/* PLLSRC: PLL entry clock source */
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#define RCC_CFGR_PLLSRC_HSI_CLK_DIV2 0x0
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#define RCC_CFGR_PLLSRC_HSE_CLK 0x1
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/* ADCPRE: ADC prescaler */
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/****************************************************************************/
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#define RCC_CFGR_ADCPRE_PCLK2_DIV2 0x0
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#define RCC_CFGR_ADCPRE_PCLK2_DIV4 0x1
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#define RCC_CFGR_ADCPRE_PCLK2_DIV6 0x2
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#define RCC_CFGR_ADCPRE_PCLK2_DIV8 0x3
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/* PPRE2: APB high-speed prescaler (APB2) */
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#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0
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#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4
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#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5
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#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6
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#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7
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/* PPRE1: APB low-speed prescaler (APB1) */
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#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0
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#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4
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#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5
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#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6
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#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7
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/* HPRE: AHB prescaler */
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#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0
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#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8
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#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9
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#define RCC_CFGR_HPRE_SYSCLK_DIV8 0xa
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#define RCC_CFGR_HPRE_SYSCLK_DIV16 0xb
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#define RCC_CFGR_HPRE_SYSCLK_DIV64 0xc
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#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd
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#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe
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#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf
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/* SWS: System clock switch status */
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#define RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x0
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#define RCC_CFGR_SWS_SYSCLKSEL_HSECLK 0x1
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#define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x2
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/* SW: System clock switch */
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#define RCC_CFGR_SW_SYSCLKSEL_HSICLK 0x0
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#define RCC_CFGR_SW_SYSCLKSEL_HSECLK 0x1
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#define RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x2
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/* --- RCC_CIR values ------------------------------------------------------ */
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/* Clock security system interrupt clear bit */
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#define RCC_CIR_CSSC (1 << 23)
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/* OSC ready interrupt clear bits */
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#define RCC_CIR_HSI14RDYC (1 << 21)
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#define RCC_CIR_PLLRDYC (1 << 20)
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#define RCC_CIR_HSERDYC (1 << 19)
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#define RCC_CIR_HSIRDYC (1 << 18)
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#define RCC_CIR_LSERDYC (1 << 17)
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#define RCC_CIR_LSIRDYC (1 << 16)
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/* OSC ready interrupt enable bits */
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#define RCC_CIR_HSI14RDYIE (1 << 13)
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#define RCC_CIR_PLLRDYIE (1 << 12)
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#define RCC_CIR_HSERDYIE (1 << 11)
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#define RCC_CIR_HSIRDYIE (1 << 10)
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#define RCC_CIR_LSERDYIE (1 << 9)
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#define RCC_CIR_LSIRDYIE (1 << 8)
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/* Clock security system interrupt flag bit */
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#define RCC_CIR_CSSF (1 << 7)
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/* OSC ready interrupt flag bits */
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#define RCC_CIR_HSI14RDYF (1 << 5)
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#define RCC_CIR_PLLRDYF (1 << 4)
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#define RCC_CIR_HSERDYF (1 << 3)
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#define RCC_CIR_HSIRDYF (1 << 2)
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#define RCC_CIR_LSERDYF (1 << 1)
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#define RCC_CIR_LSIRDYF (1 << 0)
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/* --- RCC_APB2RSTR values ------------------------------------------------- */
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#define RCC_APB2RSTR_TIM17RST (1 << 18)
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#define RCC_APB2RSTR_TIM16RST (1 << 17)
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#define RCC_APB2RSTR_TIM15RST (1 << 16)
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#define RCC_APB2RSTR_USART1RST (1 << 14)
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#define RCC_APB2RSTR_SPI1RST (1 << 12)
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#define RCC_APB2RSTR_TIM1RST (1 << 11)
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#define RCC_APB2RSTR_ADCRST (1 << 9)
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#define RCC_APB2RSTR_SYSCFGRST (1 << 0)
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/* --- RCC_APB1RSTR values ------------------------------------------------- */
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#define RCC_APB1RSTR_CECRST (1 << 30)
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#define RCC_APB1RSTR_DACRST (1 << 29)
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#define RCC_APB1RSTR_PWRRST (1 << 28)
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#define RCC_APB1RSTR_USBRST (1 << 23)
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#define RCC_APB1RSTR_I2C2RST (1 << 22)
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#define RCC_APB1RSTR_I2C1RST (1 << 21)
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#define RCC_APB1RSTR_USART2RST (1 << 17)
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#define RCC_APB1RSTR_SPI3RST (1 << 15)
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#define RCC_APB1RSTR_SPI2RST (1 << 14)
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#define RCC_APB1RSTR_WWDGRST (1 << 11)
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#define RCC_APB1RSTR_TIM14RST (1 << 8)
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#define RCC_APB1RSTR_TIM6RST (1 << 4)
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#define RCC_APB1RSTR_TIM3RST (1 << 1)
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#define RCC_APB1RSTR_TIM2RST (1 << 0)
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/* --- RCC_AHBENR values --------------------------------------------------- */
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#define RCC_AHBENR_TSCEN (1 << 24)
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#define RCC_AHBENR_GPIOFEN (1 << 22)
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#define RCC_AHBENR_GPIOEEN (1 << 21)
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#define RCC_AHBENR_GPIODEN (1 << 20)
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#define RCC_AHBENR_GPIOCEN (1 << 19)
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#define RCC_AHBENR_GPIOBEN (1 << 18)
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#define RCC_AHBENR_GPIOAEN (1 << 17)
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#define RCC_AHBENR_CRCEN (1 << 6)
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#define RCC_AHBENR_FLTFEN (1 << 4)
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#define RCC_AHBENR_SRAMEN (1 << 2)
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#define RCC_AHBENR_DMAEN (1 << 0)
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/* --- RCC_APB2ENR values -------------------------------------------------- */
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#define RCC_APB2ENR_TIM17EN (1 << 18)
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#define RCC_APB2ENR_TIM16EN (1 << 17)
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#define RCC_APB2ENR_TIM15EN (1 << 16)
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#define RCC_APB2ENR_USART1EN (1 << 14)
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#define RCC_APB2ENR_SPI1EN (1 << 12)
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#define RCC_APB2ENR_TIM1EN (1 << 11)
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#define RCC_APB2ENR_ADCEN (1 << 9)
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#define RCC_APB2ENR_SYSCFGCOMPEN (1 << 0)
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/* --- RCC_APB1ENR values -------------------------------------------------- */
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#define RCC_APB1ENR_CECEN (1 << 30)
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#define RCC_APB1ENR_DACEN (1 << 29)
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#define RCC_APB1ENR_PWREN (1 << 28)
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#define RCC_APB1ENR_USBEN (1 << 23)
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#define RCC_APB1ENR_I2C2EN (1 << 22)
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#define RCC_APB1ENR_I2C1EN (1 << 21)
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#define RCC_APB1ENR_USART2EN (1 << 17)
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#define RCC_APB1ENR_SPI3EN (1 << 15)
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#define RCC_APB1ENR_SPI2EN (1 << 14)
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#define RCC_APB1ENR_WWDGEN (1 << 11)
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#define RCC_APB1ENR_TIM14EN (1 << 8)
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#define RCC_APB1ENR_TIM6EN (1 << 4)
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#define RCC_APB1ENR_TIM3EN (1 << 1)
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#define RCC_APB1ENR_TIM2EN (1 << 0)
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/* --- RCC_BDCR values ----------------------------------------------------- */
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#define RCC_BDCR_BDRST (1 << 16)
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#define RCC_BDCR_RTCEN (1 << 15)
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/* RCC_BDCR[9:8]: RTCSEL */
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#define RCC_BDCR_LSEBYP (1 << 2)
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#define RCC_BDCR_LSERDY (1 << 1)
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#define RCC_BDCR_LSEON (1 << 0)
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/* --- RCC_CSR values ------------------------------------------------------ */
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#define RCC_CSR_LPWRRSTF (1 << 31)
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#define RCC_CSR_WWDGRSTF (1 << 30)
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#define RCC_CSR_IWDGRSTF (1 << 29)
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#define RCC_CSR_SFTRSTF (1 << 28)
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#define RCC_CSR_PORRSTF (1 << 27)
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#define RCC_CSR_PINRSTF (1 << 26)
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#define RCC_CSR_RMVF (1 << 24)
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#define RCC_CSR_LSIRDY (1 << 1)
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#define RCC_CSR_LSION (1 << 0)
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/* --- RCC_AHBRSTR values -------------------------------------------------- */
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#define RCC_AHBRSTR_ETHMACRST (1 << 14)
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#define RCC_AHBRSTR_OTGFSRST (1 << 12)
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/* --- RCC_CFGR2 values ---------------------------------------------------- */
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#define RCC_CFGR2_PREDIV 0xf
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#define RCC_CFGR2_PREDIV_NODIV 0x0
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#define RCC_CFGR2_PREDIV_DIV2 0x1
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#define RCC_CFGR2_PREDIV_DIV3 0x2
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#define RCC_CFGR2_PREDIV_DIV4 0x3
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#define RCC_CFGR2_PREDIV_DIV5 0x4
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#define RCC_CFGR2_PREDIV_DIV6 0x5
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#define RCC_CFGR2_PREDIV_DIV7 0x6
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#define RCC_CFGR2_PREDIV_DIV8 0x7
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#define RCC_CFGR2_PREDIV_DIV9 0x8
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#define RCC_CFGR2_PREDIV_DIV10 0x9
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#define RCC_CFGR2_PREDIV_DIV11 0xa
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#define RCC_CFGR2_PREDIV_DIV12 0xb
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#define RCC_CFGR2_PREDIV_DIV13 0xc
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#define RCC_CFGR2_PREDIV_DIV14 0xd
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#define RCC_CFGR2_PREDIV_DIV15 0xe
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#define RCC_CFGR2_PREDIV_DIV16 0xf
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/* --- RCC_CFGR3 values ---------------------------------------------------- */
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#define RCC_CFGR3_USART2SW_SHIFT 16
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#define RCC_CFGR3_USART2SW (3 << RCC_CFGR3_USART2SW_SHIFT)
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#define RCC_CFGR3_USART2SW_PCLK (0 << RCC_CFGR3_USART2SW_SHIFT)
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#define RCC_CFGR3_USART2SW_SYSCLK (1 << RCC_CFGR3_USART2SW_SHIFT)
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#define RCC_CFGR3_USART2SW_LSE (2 << RCC_CFGR3_USART2SW_SHIFT)
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#define RCC_CFGR3_USART2SW_HSI (3 << RCC_CFGR3_USART2SW_SHIFT)
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#define RCC_CFGR3_ADCSW (1 << 8)
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#define RCC_CFGR3_CECSW (1 << 6)
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/* --- Variable definitions ------------------------------------------------ */
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extern uint32_t rcc_ahb_frequency;
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extern uint32_t rcc_apb1_frequency;
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extern uint32_t rcc_apb2_frequency;
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/* --- Function prototypes ------------------------------------------------- */
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enum rcc_clock_hsi {
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RCC_CLOCK_HSI_48MHZ,
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RCC_CLOCK_HSI_64MHZ,
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RCC_CLOCK_HSI_END
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};
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enum rcc_clock_hse8 {
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RCC_CLOCK_HSE8_72MHZ,
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RCC_CLOCK_HSE8_END
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};
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struct rcc_clock_scale {
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uint8_t pllmul;
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uint8_t hpre;
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uint8_t ppre1;
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uint8_t ppre2;
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uint8_t adcpre;
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uint8_t usbpre; /* Only valid if HSE used */
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bool use_hse; /* PLL source is HSE if set, HSI/2 if unset */
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uint8_t pll_hse_prediv; /* Only valid if HSE used */
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uint32_t ahb_frequency;
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uint32_t apb1_frequency;
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uint32_t apb2_frequency;
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};
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extern const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_HSI_END];
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extern const struct rcc_clock_scale rcc_hse8_configs[RCC_CLOCK_HSE8_END];
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enum rcc_osc {
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RCC_PLL, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI
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};
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#define _REG_BIT(base, bit) (((base) << 5) + (bit))
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/* V = value line F100
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* N = standard line F101, F102, F103
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* C = communication line F105, F107
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*/
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enum rcc_periph_clken {
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/* AHB peripherals */
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RCC_DMA = _REG_BIT(0x14, 0),
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RCC_SRAM = _REG_BIT(0x14, 2),
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RCC_FLTF = _REG_BIT(0x14, 4),
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RCC_CRC = _REG_BIT(0x14, 6),
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RCC_GPIOA = _REG_BIT(0x14, 17),
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RCC_GPIOB = _REG_BIT(0x14, 18),
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RCC_GPIOC = _REG_BIT(0x14, 19),
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RCC_GPIOD = _REG_BIT(0x14, 20),
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RCC_GPIOF = _REG_BIT(0x14, 22),
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RCC_TSC = _REG_BIT(0x14, 24),
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/* APB2 peripherals */
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RCC_SYSCFG_COMP = _REG_BIT(0x18, 0),
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RCC_ADC = _REG_BIT(0x18, 9),
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RCC_TIM1 = _REG_BIT(0x18, 11),
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RCC_SPI1 = _REG_BIT(0x18, 12),
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RCC_USART1 = _REG_BIT(0x18, 14),
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RCC_TIM15 = _REG_BIT(0x18, 16),
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RCC_TIM16 = _REG_BIT(0x18, 17),
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RCC_TIM17 = _REG_BIT(0x18, 18),
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/* APB1 peripherals */
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RCC_TIM2 = _REG_BIT(0x1C, 0),
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RCC_TIM3 = _REG_BIT(0x1C, 1),
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RCC_TIM6 = _REG_BIT(0x1C, 4),
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RCC_TIM14 = _REG_BIT(0x1C, 8),
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RCC_WWDG = _REG_BIT(0x1C, 11),
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RCC_SPI2 = _REG_BIT(0x1C, 14),
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RCC_SPI3 = _REG_BIT(0x1C, 15),
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RCC_USART2 = _REG_BIT(0x1C, 17),
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RCC_I2C1 = _REG_BIT(0x1C, 21),
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RCC_I2C2 = _REG_BIT(0x1C, 22),
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RCC_USB = _REG_BIT(0x1C, 23),
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RCC_PWR = _REG_BIT(0x1C, 28),
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RCC_DAC = _REG_BIT(0x1C, 29),
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RCC_CEC = _REG_BIT(0x1C, 30),
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};
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enum rcc_periph_rst {
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/* Advanced peripherals */
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RST_BACKUPDOMAIN = _REG_BIT(0x20, 16),/* BDCR[16] */
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/* AHB peripherals */
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RST_GPIOA = _REG_BIT(0x28, 17),
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RST_GPIOB = _REG_BIT(0x28, 18),
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RST_GPIOC = _REG_BIT(0x28, 19),
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RST_GPIOD = _REG_BIT(0x28, 20),
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RST_GPIOE = _REG_BIT(0x28, 21),
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RST_GPIOF = _REG_BIT(0x28, 22),
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RST_TSC = _REG_BIT(0x28, 24),
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/* APB2 peripherals */
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RST_SYSCFG = _REG_BIT(0x0C, 0),
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RST_ADC = _REG_BIT(0x0C, 9),
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RST_TIM1 = _REG_BIT(0x0C, 11),
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RST_SPI1 = _REG_BIT(0x0C, 12),
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RST_USART1 = _REG_BIT(0x0C, 14),
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RST_TIM15 = _REG_BIT(0x0C, 16),
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RST_TIM16 = _REG_BIT(0x0C, 17),
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RST_TIM17 = _REG_BIT(0x0C, 18),
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/* APB1 peripherals */
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RST_TIM2 = _REG_BIT(0x10, 0),
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RST_TIM3 = _REG_BIT(0x10, 1),
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RST_TIM6 = _REG_BIT(0x10, 4),
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RST_TIM14 = _REG_BIT(0x10, 8),
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RST_WWDG = _REG_BIT(0x10, 11),
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RST_SPI2 = _REG_BIT(0x10, 14),
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RST_SPI3 = _REG_BIT(0x10, 15),
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RST_USART2 = _REG_BIT(0x10, 17),
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RST_I2C1 = _REG_BIT(0x10, 21),
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RST_I2C2 = _REG_BIT(0x10, 22),
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RST_USB = _REG_BIT(0x10, 23),
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RST_PWR = _REG_BIT(0x10, 28),
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RST_DAC = _REG_BIT(0x10, 29),
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RST_CEC = _REG_BIT(0x10, 30),
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};
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#include <libopencm3/stm32/common/rcc_common_all.h>
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BEGIN_DECLS
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void rcc_osc_ready_int_clear(enum rcc_osc osc);
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void rcc_osc_ready_int_enable(enum rcc_osc osc);
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void rcc_osc_ready_int_disable(enum rcc_osc osc);
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int rcc_osc_ready_int_flag(enum rcc_osc osc);
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void rcc_css_int_clear(void);
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int rcc_css_int_flag(void);
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void rcc_osc_on(enum rcc_osc osc);
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void rcc_osc_off(enum rcc_osc osc);
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void rcc_css_enable(void);
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void rcc_css_disable(void);
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void rcc_set_sysclk_source(uint32_t clk);
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void rcc_set_pll_multiplication_factor(uint32_t mul);
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void rcc_set_pll_source(uint32_t pllsrc);
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void rcc_set_pllxtpre(uint32_t pllxtpre);
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uint32_t rcc_rtc_clock_enabled_flag(void);
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void rcc_enable_rtc_clock(void);
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void rcc_set_rtc_clock_source(enum rcc_osc clock_source);
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void rcc_set_adcpre(uint32_t adcpre);
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void rcc_set_ppre2(uint32_t ppre1);
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void rcc_set_ppre1(uint32_t ppre1);
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void rcc_set_hpre(uint32_t hpre);
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void rcc_set_usbpre(uint32_t usbpre);
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void rcc_set_prediv(uint32_t prediv);
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uint32_t rcc_system_clock_source(void);
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void rcc_clock_setup_pll(const struct rcc_clock_scale *clock);
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void rcc_backupdomain_reset(void);
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END_DECLS
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#endif
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/**@}*/
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