139 lines
4.1 KiB
C
139 lines
4.1 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2015 Felix Held <felix-libopencm3@felixheld.de>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_PMC_H
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#define LIBOPENCM3_PMC_H
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#include <libopencm3/sam/memorymap.h>
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#include <libopencm3/sam/common/pmc_common_all.h>
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#include <libopencm3/sam/common/pmc_common_3a3s3x.h>
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/* --- Power Management Controller (PMC) registers ----------------------- */
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/* PLLB Register */
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#define CKGR_PLLBR MMIO32(PMC_BASE + 0x002C)
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/* Oscillator Calibration Register */
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#define PMC_OCR MMIO32(PMC_BASE + 0x0110)
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/* --- Register contents --------------------------------------------------- */
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/* --- PMC Clock Generator Main Clock Frequency Register (CKGR_MCFR) ------- */
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/* RC Oscillator Frequency Measure (write-only, only on atsam3s8) */
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#define CKGR_MCFR_RCMEAS (0x01 << 20)
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/* --- PMC Clock Generator PLLB Register (CKGR_PLLBR) ---------------------- */
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/* PLLB Multiplier */
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#define CKGR_PLLBR_MULB_SHIFT 16
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#define CKGR_PLLBR_MULB_MASK (0x7FF << CKGR_PLLBR_MULB_SHIFT)
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/* PLLA Counter */
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#define CKGR_PLLBR_PLLBCOUNT_SHIFT 8
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#define CKGR_PLLBR_PLLBCOUNT_MASK (0x3F << CKGR_PLLBR_PLLBCOUNT_SHIFT)
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/* Divider */
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#define CKGR_PLLBR_DIVB_SHIFT 0
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#define CKGR_PLLBR_DIVB_MASK (0xFF << CKGR_PLLBR_DIVB_SHIFT)
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/* --- PMC Master Clock Register (PMC_MCKR) -------------------------------- */
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/* PLLB Divide by 2 */
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#define PMC_MCKR_PLLBDIV2 (0x01 << 13)
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/* PLLA Divide by 2 */
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#define PMC_MCKR_PLLADIV2 (0x01 << 12)
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/* Master Clock Source Selection */
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#define PMC_MCKR_CSS_PLLB_CLK (3 << PMC_MCKR_CSS_SHIFT)
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/* --- PMC Programmable Clock Register 0 (PMC_PCK0) ------------------------ */
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/* Master Clock Source Selection */
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#define PMC_PCK0_CSS_PLLB_CLK (3 << PMC_PCK0_CSS_SHIFT)
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/* --- PMC Programmable Clock Register 1 (PMC_PCK1) ------------------------ */
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/* Master Clock Source Selection */
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#define PMC_PCK1_CSS_PLLB_CLK (3 << PMC_PCK1_CSS_SHIFT)
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/* --- PMC Programmable Clock Register 2 (PMC_PCK2) ------------------------ */
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/* Master Clock Source Selection */
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#define PMC_PCK2_CSS_PLLB_CLK (3 << PMC_PCK2_CSS_SHIFT)
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/* --- PMC Interrupt Enable Register (PMC_IER) ----------------------------- */
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/* PLLB Lock Interrupt Enable */
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#define PMC_IER_LOCKB (0x01 << 2)
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/* --- PMC Interrupt Disable Register (PMC_IDR) ---------------------------- */
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/* PLLB Lock Interrupt Disable */
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#define PMC_IDR_LOCKB (0x01 << 2)
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/* --- PMC Status Register (PMC_SR) ---------------------------------------- */
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/* PLLB Lock Status */
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#define PMC_SR_LOCKB (0x01 << 2)
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/* --- PMC Interrupt Mask Register (PMC_IDR) ------------------------------- */
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/* PLLB Lock Interrupt Mask */
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#define PMC_IMR_LOCKB (0x01 << 2)
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/* --- PMC Oscillator Calibration Register (PMC_OCR) ----------------------- */
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/* Selection of RC Oscillator Calibration bits for 12 Mhz */
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#define PMC_OCR_SEL12 (0x01 << 23)
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/* RC Oscillator Calibration bits for 12 Mhz */
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#define PMC_OCR_CAL12_SHIFT 16
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#define PMC_OCR_CAL12_MASK (0x7F << PMC_OCR_CAL12_SHIFT)
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/* Selection of RC Oscillator Calibration bits for 8 Mhz */
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#define PMC_OCR_SEL8 (0x01 << 15)
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/* RC Oscillator Calibration bits for 8 Mhz */
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#define PMC_OCR_CAL8_SHIFT 8
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#define PMC_OCR_CAL8_MASK (0x7F << PMC_OCR_CAL8_SHIFT)
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/* Selection of RC Oscillator Calibration bits for 4 Mhz */
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#define PMC_OCR_SEL4 (0x01 << 7)
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/* RC Oscillator Calibration bits for 4 Mhz */
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#define PMC_OCR_CAL4_SHIFT 0
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#define PMC_OCR_CAL4_MASK (0x7F << PMC_OCR_CAL12_SHIFT)
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#endif
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