205 lines
6.0 KiB
C
205 lines
6.0 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2015 Felix Held <felix-libopencm3@felixheld.de>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_SMC_H
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#define LIBOPENCM3_SMC_H
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#include <libopencm3/sam/memorymap.h>
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/* Chip Select Defines */
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#define SMC_CS_0 0
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#define SMC_CS_1 1
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#define SMC_CS_2 2
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#define SMC_CS_3 3
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/* --- Static Memory Controller (SMC) registers ---------------------------- */
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/* Setup Register */
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#define SMC_SETUP(CS_number) MMIO32(SMC_BASE + 0x10*(CS_number) \
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+ 0x00)
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/* Pulse Register */
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#define SMC_PULSE(CS_number) MMIO32(SMC_BASE + 0x10*(CS_number) \
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+ 0x04)
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/* Cycle Register */
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#define SMC_CYCLE(CS_number) MMIO32(SMC_BASE + 0x10*(CS_number) \
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+ 0x08)
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/* Mode Register */
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#define SMC_MODE(CS_number) MMIO32(SMC_BASE + 0x10*(CS_number) \
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+ 0x0C)
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/* Off Chip Memory Scrambling Mode Register */
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#define SMC_OCMS MMIO32(SMC_BASE + 0x80)
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/* Off Chip Memory Scrambling KEY1 Register */
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#define SMC_KEY1 MMIO32(SMC_BASE + 0x84)
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/* Off Chip Memory Scrambling KEY2 Register */
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#define SMC_KEY2 MMIO32(SMC_BASE + 0x88)
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/* Write Protect Mode Register */
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#define SMC_WPMR MMIO32(SMC_BASE + 0xE4)
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/* Write Protect Status Register */
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#define SMC_WPSR MMIO32(SMC_BASE + 0xE8)
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/* --- Register contents --------------------------------------------------- */
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/* --- SMC Setup Register (SMC_SETUPx) ------------------------------------- */
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/* NCS Setup length in Read access */
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#define SMC_SETUP_NCS_RD_SETUP_SHIFT 24
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#define SMC_SETUP_NCS_RD_SETUP_MASK (0x3F << SMC_SETUP_NCS_RD_SETUP_SHIFT)
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/* NRD Setup length */
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#define SMC_SETUP_NRD_SETUP_SHIFT 16
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#define SMC_SETUP_NRD_SETUP_MASK (0x3F << SMC_SETUP_NRD_SETUP_SHIFT)
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/* NCS Setup length in Write access */
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#define SMC_SETUP_NCS_WR_SETUP_SHIFT 8
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#define SMC_SETUP_NCS_WR_SETUP_MASK (0x3F << SMC_SETUP_NCS_WR_SETUP_SHIFT)
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/* NWE Setup Length */
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#define SMC_SETUP_NWE_SETUP_SHIFT 0
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#define SMC_SETUP_NWE_SETUP_MASK (0x3F << SMC_SETUP_NWE_SETUP_SHIFT)
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/* --- SMC Pulse Register (SMC_PULSEx) ------------------------------------- */
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/* NCS Pulse Length in READ Access */
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#define SMC_PULSE_NCS_RD_PULSE_SHIFT 24
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#define SMC_PULSE_NCS_RD_PULSE_MASK (0x7F << SMC_PULSE_NCS_RD_PULSE_SHIFT)
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/* NRD Pulse Length */
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#define SMC_PULSE_NRD_PULSE_SHIFT 16
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#define SMC_PULSE_NRD_PULSE_MASK (0x7F << SMC_PULSE_NRD_PULSE_SHIFT)
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/* NCS Pulse Length in WRITE Access */
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#define SMC_PULSE_NCS_WR_PULSE_SHIFT 8
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#define SMC_PULSE_NCS_WR_PULSE_MASK (0x7F << SMC_PULSE_NCS_WR_PULSE_SHIFT)
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/* NWE Pulse Length */
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#define SMC_PULSE_NWE_PULSE_SHIFT 0
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#define SMC_PULSE_NWE_PULSE_MASK (0x7F << SMC_PULSE_NWE_PULSE_SHIFT)
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/* --- SMC Cycle Register (SMC_CYCLEx) ------------------------------------- */
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/* Total Read Cycle Length */
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#define SMC_CYCLE_NRD_CYCLE_SHIFT 16
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#define SMC_CYCLE_NRD_CYCLE_MASK (0x1FF << SMC_CYCLE_NRD_CYCLE_SHIFT)
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/* Total Write Cycle Length */
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#define SMC_CYCLE_NWE_CYCLE_SHIFT 0
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#define SMC_CYCLE_NWE_CYCLE_MASK (0x1FF << SMC_CYCLE_NWE_CYCLE_SHIFT)
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/* --- SMC MODE Register (SMC_MODEx) --------------------------------------- */
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/* Page Size */
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#define SMC_MODE_PS_SHIFT 28
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#define SMC_MODE_PS_MASK (0x03 << SMC_MODE_PS_SHIFT)
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/* Page Size Values */
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#define SMC_MODE_PS_4_BYTE (0x00 << SMC_MODE_PS_SHIFT)
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#define SMC_MODE_PS_8_BYTE (0x01 << SMC_MODE_PS_SHIFT)
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#define SMC_MODE_PS_16_BYTE (0x02 << SMC_MODE_PS_SHIFT)
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#define SMC_MODE_PS_32_BYTE (0x03 << SMC_MODE_PS_SHIFT)
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/* Page Mode Enabled */
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#define SMC_MODE_PMEN (1 << 24)
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/* TDF Optimization */
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#define SMC_MODE_TDF_MODE (1 << 20)
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/* Data Float Time */
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#define SMC_MODE_TDF_CYCLES_SHIFT 16
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#define SMC_MODE_TDF_CYCLES_MASK (0x0F << SMC_MODE_TDF_CYCLES_SHIFT)
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/* Data Bus Width */
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#define SMC_MODE_DBW_SHIFT 12
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#define SMC_MODE_DBW_MASK (0x03 << SMC_MODE_DBW_SHIFT)
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/* Data Bus Width Values */
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#define SMC_MODE_DBW_8_BIT (0x00 << SMC_MODE_DBW_SHIFT)
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#define SMC_MODE_DBW_16_BIT (0x01 << SMC_MODE_DBW_SHIFT)
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#define SMC_MODE_DBW_32_BIT (0x02 << SMC_MODE_DBW_SHIFT)
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/* NWAIT Mode */
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#define SMC_MODE_EXNW_MODE_SHIFT 4
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#define SMC_MODE_EXNW_MODE_MASK (0x03 << SMC_MODE_EXNW_MODE_SHIFT)
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/* NWAIT Mode Values */
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#define SMC_MODE_EXNW_MODE_DISABLED (0x00 << SMC_MODE_EXNW_MODE_SHIFT)
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#define SMC_MODE_EXNW_MODE_FROZEN (0x02 << SMC_MODE_EXNW_MODE_SHIFT)
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#define SMC_MODE_EXNW_MODE_READY (0x03 << SMC_MODE_EXNW_MODE_SHIFT)
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/* Write Mode */
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#define SMC_MODE_WRITE_MODE (1 << 1)
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/* Read Mode */
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#define SMC_MODE_READ_MODE (1 << 0)
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/* --- SMC OCMS Mode Register (SMC_OCMS) ----------------------------------- */
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/* Chip Select 3 Scrambling Enable */
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#define SMC_OCMS_CS3SE (1 << 19)
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/* Chip Select 2 Scrambling Enable */
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#define SMC_OCMS_CS2SE (1 << 18)
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/* Chip Select 1 Scrambling Enable */
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#define SMC_OCMS_CS1SE (1 << 17)
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/* Chip Select 0 Scrambling Enable */
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#define SMC_OCMS_CS0SE (1 << 16)
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/* Static Memory Controller Scrambling Enable */
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#define SMC_OCMS_SMSE (1 << 0)
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/* --- SMC Write Protect Mode Register (SMC_WPMR) -------------------------- */
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/* Write Protect Key */
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#define SMC_WPMR_WPKEY_SHIFT 8
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#define SMC_WPMR_WPKEY_KEY (0x534D43 << SMC_WPMR_WPKEY_SHIFT)
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/* Write Protect Enable */
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#define SMC_WPMR_WPEN (1 << 0)
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/* --- SMC Write Protect Status Register (SMC_WPSR) ------------------------ */
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/* Write Protection Violation Source */
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#define SMC_WPSR_WP_VSRC_SHIFT 8
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#define SMC_WPSR_WP_VSRC_MASK (0xFFFF << SMC_WPSR_WP_VSRC_SHIFT)
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/* Write Protect Enable */
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#define SMC_WPSR_WPVS (1 << 0)
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#endif
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