54eff24e7c
SWM050 is a series of MCU made by Foshan Synwit Tech. It contains a Cortex-M0 CPU core, 8KiB of Flash and 1KiB of SRAM. The only peripherals are GPIO, Timer and WDT. There's only two parts in this series, with either TSSOP-8 or SSOP-16 packages. This commit introduces the interrupt vector and GPIO support for them. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
36 lines
1.2 KiB
C
36 lines
1.2 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_MEMORYMAP_H
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#define LIBOPENCM3_MEMORYMAP_H
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#include <libopencm3/cm3/memorymap.h>
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/* Memory map for all buses */
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#define PERIPH_BASE (0x40000000U)
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#define SYSTEM_CON_BASE (PERIPH_BASE + 0x0)
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#define GPIO_BASE (PERIPH_BASE + 0x1000)
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#define TIMER_SE0_BASE (PERIPH_BASE + 0x2000)
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#define TIMER_SE1_BASE (PERIPH_BASE + 0x2400)
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#define WDT_BASE (PERIPH_BASE + 0x19000)
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#define SYSCTL_BASE (PERIPH_BASE + 0xf0000)
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#endif
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