7df63fcae0
Added --terse and --mailback options to the make stylecheck target. It also does continue even if it enounters a possible error. We decided on two exceptions from the linux kernel coding standard: - Empty wait while loops may end with ; on the same line. - All blocks after while, if, for have to be in brackets even if they only contain one statement. Otherwise it is easy to introduce an error. Checkpatch needs to be adapted to reflect those changes.
105 lines
3.4 KiB
C
105 lines
3.4 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_CM3_TPIU_H
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#define LIBOPENCM3_CM3_TPIU_H
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/* Cortex-M3 Trace Port Interface Unit (TPIU) */
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/* --- TPIU registers ------------------------------------------------------ */
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/* Supported Synchronous Port Size (TPIU_SSPSR) */
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#define TPIU_SSPSR MMIO32(TPIU_BASE + 0x000)
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/* Current Synchronous Port Size (TPIU_CSPSR) */
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#define TPIU_CSPSR MMIO32(TPIU_BASE + 0x004)
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/* Asynchronous Clock Prescaler (TPIU_ACPR) */
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#define TPIU_ACPR MMIO32(TPIU_BASE + 0x010)
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/* Selected Pin Protocol (TPIU_SPPR) */
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#define TPIU_SPPR MMIO32(TPIU_BASE + 0x0F0)
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/* Formatter and Flush Status Register (TPIU_FFSR) */
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#define TPIU_FFSR MMIO32(TPIU_BASE + 0x300)
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/* Formatter and Flush Control Register (TPIU_FFCR) */
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#define TPIU_FFCR MMIO32(TPIU_BASE + 0x304)
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/* (TPIU_DEVID) */
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#define TPIU_DEVID MMIO32(TPIU_BASE + 0xFC8)
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/* TODO: PID, CID */
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/* --- TPIU_SSPSR values --------------------------------------------------- */
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/*
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* bit[N] == 0, trace port width of (N+1) not supported
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* bit[N] == 1, trace port width of (N+1) supported
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*/
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#define TPIU_SSPSR_BYTE (1 << 0)
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#define TPIU_SSPSR_HALFWORD (1 << 1)
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#define TPIU_SSPSR_WORD (1 << 3)
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/* --- TPIU_SSPSR values --------------------------------------------------- */
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/* Same format as TPIU_SSPSR, except only one is set */
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#define TPIU_CSPSR_BYTE (1 << 0)
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#define TPIU_CSPSR_HALFWORD (1 << 1)
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#define TPIU_CSPSR_WORD (1 << 3)
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/* --- TPIU_ACPR values ---------------------------------------------------- */
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/* Bits 31:16 - Reserved */
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/* Bits 15:0 - SWO output clock = Asynchronous_Reference_Clock/(value +1) */
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/* --- TPIU_SPPR values ---------------------------------------------------- */
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/* Bits 31:2 - Reserved */
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#define TPIU_SPPR_SYNC (0x0)
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#define TPIU_SPPR_ASYNC_MANCHESTER (0x1)
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#define TPIU_SPPR_ASYNC_NRZ (0x2)
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/* --- TPIU_FFSR values ---------------------------------------------------- */
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/* Bits 31:4 - Reserved */
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#define TPIU_FFSR_FTNONSTOP (1 << 3)
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#define TPIU_FFSR_TCPRESENT (1 << 2)
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#define TPIU_FFSR_FTSTOPPED (1 << 1)
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#define TPIU_FFSR_FLINPROG (1 << 0)
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/* --- TPIU_FFCR values ---------------------------------------------------- */
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/* Bits 31:9 - Reserved */
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#define TPIU_FFCR_TRIGIN (1 << 8)
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/* Bits 7:2 - Reserved */
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#define TPIU_FFCR_ENFCONT (1 << 1)
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/* Bit 0 - Reserved */
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/* --- TPIU_DEVID values ---------------------------------------------------- */
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/* Bits 31:16 - Reserved */
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/* Bits 15:12 - Implementation defined */
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#define TPUI_DEVID_NRZ_SUPPORTED (1 << 11)
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#define TPUI_DEVID_MANCHESTER_SUPPORTED (1 << 10)
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/* Bit 9 - RAZ, indicated that trace data and clock are supported */
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#define TPUI_DEVID_FIFO_SIZE_MASK (7 << 6)
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/* Bits 5:0 - Implementation defined */
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#endif
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