68 lines
2.4 KiB
C
68 lines
2.4 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_CM3_SCS_H
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#define LIBOPENCM3_CM3_SCS_H
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#define SCS_DHCSR MMIO32(SCS_BASE + 0xDF0)
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#define SCS_DCRSR MMIO32(SCS_BASE + 0xDF4)
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#define SCS_DCRDR MMIO32(SCS_BASE + 0xDF8)
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#define SCS_DEMCR MMIO32(SCS_BASE + 0xDFC)
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/* Debug Halting Control and Status Register (DHCSR) */
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#define SCS_DHCSR_DBGKEY 0xA05F0000
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#define SCS_DHCSR_C_DEBUGEN 0x00000001
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#define SCS_DHCSR_C_HALT 0x00000002
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#define SCS_DHCSR_C_STEP 0x00000004
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#define SCS_DHCSR_C_MASKINTS 0x00000008
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#define SCS_DHCSR_C_SNAPSTALL 0x00000020
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#define SCS_DHCSR_S_REGRDY 0x00010000
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#define SCS_DHCSR_S_HALT 0x00020000
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#define SCS_DHCSR_S_SLEEP 0x00040000
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#define SCS_DHCSR_S_LOCKUP 0x00080000
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#define SCS_DHCSR_S_RETIRE_ST 0x01000000
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#define SCS_DHCSR_S_RESET_ST 0x02000000
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/* Debug Core Register Selector Register (DCRSR) */
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#define SCS_DCRSR_REGSEL_MASK 0x0000001F
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#define SCS_DCRSR_REGSEL_XPSR 0x00000010
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#define SCS_DCRSR_REGSEL_MSP 0x00000011
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#define SCS_DCRSR_REGSEL_PSP 0x00000012
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/* Debug Exception and Monitor Control Register (DEMCR) */
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/* Bits 31:25 - Reserved */
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#define SCS_DEMCR_TRCENA (1 << 24)
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/* Bits 23:20 - Reserved */
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#define SCS_DEMCR_MON_REQ (1 << 19)
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#define SCS_DEMCR_MON_STEP (1 << 18)
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#define SCS_DEMCR_VC_MON_PEND (1 << 17)
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#define SCS_DEMCR_VC_MON_EN (1 << 16)
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/* Bits 15:11 - Reserved */
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#define SCS_DEMCR_VC_HARDERR (1 << 10)
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#define SCS_DEMCR_VC_INTERR (1 << 9)
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#define SCS_DEMCR_VC_BUSERR (1 << 8)
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#define SCS_DEMCR_VC_STATERR (1 << 7)
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#define SCS_DEMCR_VC_CHKERR (1 << 6)
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#define SCS_DEMCR_VC_NOCPERR (1 << 5)
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#define SCS_DEMCR_VC_MMERR (1 << 4)
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/* Bits 3:1 - Reserved */
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#define SCS_DEMCR_VC_CORERESET (1 << 0)
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#endif
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