143 lines
3.4 KiB
C
143 lines
3.4 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/stm32/f1/dma.h>
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void dma_channel_reset(u32 dma, u8 channel)
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{
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/* Disable channel. */
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DMA_CCR(dma, channel) &= ~DMA_CCR_EN;
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/* Reset config bits. */
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DMA_CCR(dma, channel) = 0;
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/* Reset data transfer number. */
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DMA_CNDTR(dma, channel) = 0;
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/* Reset peripheral address. */
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DMA_CPAR(dma, channel) = 0;
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/* Reset memory address. */
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DMA_CMAR(dma, channel) = 0;
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/* Reset interrupt flags. */
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DMA_IFCR(dma) |= DMA_IFCR_CIF(channel);
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}
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void dma_enable_mem2mem_mode(u32 dma, u8 channel)
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{
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DMA_CCR(dma, channel) |= DMA_CCR_MEM2MEM;
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DMA_CCR(dma, channel) &= ~DMA_CCR_CIRC;
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}
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void dma_set_priority(u32 dma, u8 channel, u32 prio)
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{
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DMA_CCR(dma, channel) &= ~(DMA_CCR_PL_MASK);
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DMA_CCR(dma, channel) |= prio;
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}
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void dma_set_memory_size(u32 dma, u8 channel, u32 mem_size)
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{
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DMA_CCR(dma, channel) &= ~(DMA_CCR_MSIZE_MASK);
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DMA_CCR(dma, channel) |= mem_size;
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}
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void dma_set_peripheral_size(u32 dma, u8 channel, u32 peripheral_size)
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{
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DMA_CCR(dma, channel) &= ~(DMA_CCR_PSIZE_MASK);
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DMA_CCR(dma, channel) |= peripheral_size;
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}
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void dma_enable_memory_increment_mode(u32 dma, u8 channel)
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{
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DMA_CCR(dma, channel) |= DMA_CCR_MINC;
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}
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void dma_enable_peripheral_increment_mode(u32 dma, u8 channel)
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{
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DMA_CCR(dma, channel) |= DMA_CCR_PINC;
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}
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void dma_enable_circular_mode(u32 dma, u8 channel)
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{
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DMA_CCR(dma, channel) |= DMA_CCR_CIRC;
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DMA_CCR(dma, channel) &= ~DMA_CCR_MEM2MEM;
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}
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void dma_set_read_from_peripheral(u32 dma, u8 channel)
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{
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DMA_CCR(dma, channel) &= ~DMA_CCR_DIR;
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}
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void dma_set_read_from_memory(u32 dma, u8 channel)
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{
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DMA_CCR(dma, channel) |= DMA_CCR_DIR;
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}
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void dma_enable_transfer_error_interrupt(u32 dma, u8 channel)
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{
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DMA_CCR(dma, channel) |= DMA_CCR_TEIE;
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}
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void dma_disable_transfer_error_interrupt(u32 dma, u8 channel)
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{
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DMA_CCR(dma, channel) &= ~DMA_CCR_TEIE;
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}
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void dma_enable_half_transfer_interrupt(u32 dma, u8 channel)
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{
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DMA_CCR(dma, channel) |= DMA_CCR_HTIE;
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}
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void dma_disable_half_transfer_interrupt(u32 dma, u8 channel)
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{
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DMA_CCR(dma, channel) &= ~DMA_CCR_HTIE;
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}
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void dma_enable_transfer_complete_interrupt(u32 dma, u8 channel)
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{
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DMA_CCR(dma, channel) |= DMA_CCR_TCIE;
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}
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void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel)
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{
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DMA_CCR(dma, channel) &= ~DMA_CCR_TCIE;
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}
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void dma_enable_channel(u32 dma, u8 channel)
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{
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DMA_CCR(dma, channel) |= DMA_CCR_EN;
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}
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void dma_disable_channel(u32 dma, u8 channel)
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{
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DMA_CCR(dma, channel) &= ~DMA_CCR_EN;
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}
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void dma_set_peripheral_address(u32 dma, u8 channel, u32 address)
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{
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DMA_CPAR(dma, channel) = (u32) address;
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}
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void dma_set_memory_address(u32 dma, u8 channel, u32 address)
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{
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DMA_CMAR(dma, channel) = (u32) address;
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}
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void dma_set_number_of_data(u32 dma, u8 channel, u16 number)
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{
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DMA_CNDTR(dma, channel) = number;
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}
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