ec9fc5c122
ITM Stimulus ports need to be accessible with different sizes
The amount of data written out is determined by the size of the write.
Writing a full 32 bit value when you only need 8 for printf() style
substantially reduces the available bandwidth of the SWO
Note: this is an API change for doing 32bit writes.
Old:
ITM_STIM[stimulus_port] = value
New:
ITM_STIM32(stimulus_port) = value
This api is much more in common with some of the other registers that
behave this way. As there's very little (if any) code already using
this API, it's a good time to fix it permanently.
Remove misleading ITM register definitions
ITM_SSPSR is the supported parallel trace size, in _bits_
ITM_CSPSR is in _bits_ as well. There's really no advantage in even
having these sorts of definitions in libopencm3, as these settings are
normally controlled from the debugger side, not the target itself.
Lock and lock status register definitions were added, as per ARM:
"For ARMv7-M, the component ID registers are required for the ROM table,
and the CoreSight management lock access mechanism is defined for the
DWT, ITM, FPB and TPIU blocks."
88 lines
2.9 KiB
C
88 lines
2.9 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_CM3_MEMORYMAP_H
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#define LIBOPENCM3_CM3_MEMORYMAP_H
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/* --- ARM Cortex-M0, M3 and M4 specific definitions ----------------------- */
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/* Private peripheral bus - Internal */
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#define PPBI_BASE 0xE0000000
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/* Those defined only on ARMv7 and above */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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/* ITM: Instrumentation Trace Macrocell */
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#define ITM_BASE (PPBI_BASE + 0x0000)
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/* DWT: Data Watchpoint and Trace unit */
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#define DWT_BASE (PPBI_BASE + 0x1000)
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/* FPB: Flash Patch and Breakpoint unit */
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#define FPB_BASE (PPBI_BASE + 0x2000)
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#endif
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/* PPBI_BASE + 0x3000 (0xE000 3000 - 0xE000 DFFF): Reserved */
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#define SCS_BASE (PPBI_BASE + 0xE000)
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/* PPBI_BASE + 0xF000 (0xE000 F000 - 0xE003 FFFF): Reserved */
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/* Those defined only on ARMv7 and above */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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#define TPIU_BASE (PPBI_BASE + 0x40000)
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#endif
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/* --- SCS: System Control Space --- */
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/* Those defined only on ARMv7 and above */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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/* ITR: Interrupt Type Register */
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#define ITR_BASE (SCS_BASE + 0x0000)
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#endif
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/* SYS_TICK: System Timer */
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#define SYS_TICK_BASE (SCS_BASE + 0x0010)
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/* NVIC: Nested Vector Interrupt Controller */
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#define NVIC_BASE (SCS_BASE + 0x0100)
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/* SCB: System Control Block */
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#define SCB_BASE (SCS_BASE + 0x0D00)
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#ifdef CM0_PLUS
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/* MPU: Memory protection unit */
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#define MPU_BASE (SCS_BASE + 0x0D90)
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#endif
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/* Those defined only on CM0*/
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#if defined(__ARM_ARCH_6M__)
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/* DEBUG: Debug control and configuration */
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#define DEBUG_BASE (SCS_BASE + 0x0DF0)
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#endif
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/* Those defined only on ARMv7 and above */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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/* STE: Software Trigger Interrupt Register */
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#define STIR_BASE (SCS_BASE + 0x0F00)
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/* ID: ID space */
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#define ID_BASE (SCS_BASE + 0x0FD0)
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#endif
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#endif
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