2b1ddc8490
The original submitter of this squished everything into one series, and has not returned. The code mostly appears good, and review comments were followed for the most part. The project doesn't really maintain any testing or board farm for sam3/sam4 parts, so we're going to just trust our users. Reviewed-by: Karl Palsson <karlp@tweak.net.au> sam/4l: IRQ Configuration file (irq.json) sam/4l: Basic Memory Map. sam/4l: GPIO Defines. sam/4l: GPIO Functions Added everything that needed to compile the library: Makefile, Linker Script and common includes. sam/4l: SCIF function to start OSC. sam/4l: GPIO Enable/Disable and Multiplexing configuration functions. sam/4l: PLL Clock configuration. sam/4l: Peripheral clock configuration and basic USART support. sam: USART Character length configuration. sam/4l: Generic Clock configuration functions. sam/4l: Analog to Digital Converter Interface (ADCIFE) basic support.
122 lines
2.3 KiB
C
122 lines
2.3 KiB
C
/** @addtogroup scif
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*
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* @brief <b>Access functions for the SAM4 Analog to Digital Converter Interface (ADCIFE)</b>
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* @ingroup SAM4
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* LGPL License Terms @ref lgpl_license
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* @author @htmlonly © @endhtmlonly 2016
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* Maxim Sloyko <maxims@google.com>
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*
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*/
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#include <libopencm3/sam/adcife.h>
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/** @brief Enable ADC interface. Must be done before any other configuration.
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*
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* This function does it synchronously and returns only when the interface is
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* actually enabled.
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*/
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void adcife_enable_sync(void)
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{
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ADCIFE_CR = ADCIFE_CR_EN;
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while (!(ADCIFE_SR & ADCIFE_SR_EN));
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}
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void adcife_configure(
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enum adcife_refsel ref,
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enum adcife_speed speed,
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enum adcife_clk clk,
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enum adcife_prescal prescal)
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{
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ADCIFE_CFG = ADCIFE_CFG_REFSEL_MASKED(ref)
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| ADCIFE_CFG_SPEED_MASKED(speed)
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| ADCIFE_CFG_PRESCAL_MASKED(prescal)
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| clk;
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}
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void adcife_select_channel(enum adcife_channel ad)
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{
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ADCIFE_SEQCFG |= ADCIFE_SEQCFG_MUXPOS_MASKED(ad);
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}
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void adcife_set_resolution(enum adcife_resolution res)
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{
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if (ADCIFE_RESOLUTION_12BITS == res) {
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ADCIFE_SEQCFG &= ~ADCIFE_SEQCFG_RES;
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} else {
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ADCIFE_SEQCFG |= ADCIFE_SEQCFG_RES;
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}
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}
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void adcife_select_trigger(enum adcife_trigger trig)
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{
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ADCIFE_SEQCFG &= ~ADCIFE_SEQCFG_TRGSEL_MASK;
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ADCIFE_SEQCFG |= ADCIFE_SEQCFG_TRGSEL_MASKED(trig);
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}
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void adcife_set_gain(enum adcife_gain gain)
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{
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ADCIFE_SEQCFG &= ~ADCIFE_SEQCFG_GAIN_MASK;
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ADCIFE_SEQCFG |= ADCIFE_SEQCFG_GAIN_MASKED(gain);
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}
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void adcife_set_bipolar(bool enable)
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{
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if (enable) {
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ADCIFE_SEQCFG |= ADCIFE_SEQCFG_BIPOLAR;
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} else {
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ADCIFE_SEQCFG &= ~ADCIFE_SEQCFG_BIPOLAR;
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}
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}
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void adcife_set_left_adjust(bool enable)
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{
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if (enable) {
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ADCIFE_SEQCFG |= ADCIFE_SEQCFG_HWLA;
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} else {
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ADCIFE_SEQCFG &= ~ADCIFE_SEQCFG_HWLA;
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}
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}
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void adcife_start_conversion(void)
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{
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ADCIFE_CR = ADCIFE_CR_STRIG;
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}
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void adcife_wait_conversion(void)
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{
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while (!(ADCIFE_SR & ADCIFE_SR_SEOC));
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ADCIFE_SCR = ADCIFE_SR_SEOC;
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}
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struct adcife_lcv adcife_get_lcv(void)
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{
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struct adcife_lcv res;
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res._lc_u.lcv = ADCIFE_LCV;
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return res;
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}
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void adcife_enable_interrupts(uint32_t imask)
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{
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ADCIFE_IER = imask;
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}
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void adcife_disable_interrupts(uint32_t imask)
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{
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ADCIFE_IDR = imask;
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}
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void adcife_timer_start(void)
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{
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ADCIFE_CR = ADCIFE_CR_TSTART;
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}
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void adcife_timer_stop(void)
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{
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ADCIFE_CR = ADCIFE_CR_TSTOP;
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}
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void adcife_timer_set_timeout(uint16_t timeout)
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{
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ADCIFE_TIM = timeout;
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}
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