c72f3d588a
All the macro arguments that are user supplied, or potentially, wrap properly in () as good practice. Probably missed one or two, and a lot of them are possibly unnecessary, but it's straightforward to just do it always. Fixes github issue #321
348 lines
14 KiB
C
348 lines
14 KiB
C
/** @addtogroup rtc_defines
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@author @htmlonly © @endhtmlonly 2012 Karl Palsson <karlp@tweak.net.au>
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* This covers the "version 2" RTC peripheral. This is completely different
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* to the v1 RTC periph on the F1 series devices. It has BCD counters, with
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* automatic leapyear corrections and daylight savings support.
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* This peripheral is used on the F0, F2, F3, F4 and L1 devices, though some
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* only support a subset.
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*/
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/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA RTC.H
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The order of header inclusion is important. rtc.h includes the device
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specific memorymap.h header before including this header file.*/
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/** @cond */
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#ifdef LIBOPENCM3_RTC_H
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/** @endcond */
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#ifndef LIBOPENCM3_RTC2_H
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#define LIBOPENCM3_RTC2_H
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/**@{*/
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/* RTC time register (RTC_TR) */
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#define RTC_TR MMIO32(RTC_BASE + 0x00)
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/* RTC date register (RTC_DR) */
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#define RTC_DR MMIO32(RTC_BASE + 0x04)
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/* RTC control register (RTC_CR) */
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#define RTC_CR MMIO32(RTC_BASE + 0x08)
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/* RTC initialization and status register (RTC_ISR) */
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#define RTC_ISR MMIO32(RTC_BASE + 0x0c)
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/* RTC prescaler register (RTC_PRER) */
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#define RTC_PRER MMIO32(RTC_BASE + 0x10)
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/* RTC wakeup timer register (RTC_WUTR) */
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#define RTC_WUTR MMIO32(RTC_BASE + 0x14)
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/* RTC calibration register (RTC_CALIBR) NB: see also RTC_CALR */
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#define RTC_CALIBR MMIO32(RTC_BASE + 0x18)
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/* RTC alarm X register (RTC_ALRMxR) */
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#define RTC_ALRMAR MMIO32(RTC_BASE + 0x1c)
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#define RTC_ALRMBR MMIO32(RTC_BASE + 0x20)
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/* RTC write protection register (RTC_WPR)*/
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#define RTC_WPR MMIO32(RTC_BASE + 0x24)
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/* RTC sub second register (RTC_SSR) (high and med+ only) */
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#define RTC_SSR MMIO32(RTC_BASE + 0x28)
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/* RTC shift control register (RTC_SHIFTR) (high and med+ only) */
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#define RTC_SHIFTR MMIO32(RTC_BASE + 0x2c)
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/* RTC time stamp time register (RTC_TSTR) */
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#define RTC_TSTR MMIO32(RTC_BASE + 0x30)
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/* RTC time stamp date register (RTC_TSDR) */
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#define RTC_TSDR MMIO32(RTC_BASE + 0x34)
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/* RTC timestamp sub second register (RTC_TSSSR) (high and med+ only) */
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#define RTC_TSSSR MMIO32(RTC_BASE + 0x38)
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/* RTC calibration register (RTC_CALR) (high and med+ only) */
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#define RTC_CALR MMIO32(RTC_BASE + 0x3c)
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/* RTC tamper and alternate function configuration register (RTC_TAFCR) */
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#define RTC_TAFCR MMIO32(RTC_BASE + 0x40)
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/* RTC alarm X sub second register (RTC_ALRMxSSR) (high and med+ only) */
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#define RTC_ALRMASSR MMIO32(RTC_BASE + 0x44)
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#define RTC_ALRMBSSR MMIO32(RTC_BASE + 0x48)
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/* RTC backup registers (RTC_BKPxR) */
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#define RTC_BKP_BASE (RTC_BASE + 0x50)
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#define RTC_BKPXR(reg) MMIO32(RTC_BKP_BASE + (4 * (reg)))
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/* RTC time register (RTC_TR) ----------------------------------- */
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/* Note: Bits [31:23], 15, and 7 are reserved, and must be kept at reset value.
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*/
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#define RTC_TR_PM (1 << 22) /* AM/PM notation */
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#define RTC_TR_HT_SHIFT (20) /* Hour tens in BCD format shift */
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#define RTC_TR_HT_MASK (0x3) /* Hour tens in BCD format mask */
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#define RTC_TR_HU_SHIFT (16) /* Hour units in BCD format shift */
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#define RTC_TR_HU_MASK (0xf) /* Hour units in BCD format mask */
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#define RTC_TR_MNT_SHIFT (12) /* Minute tens in BCD format shift */
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#define RTC_TR_MNT_MASK (0x7) /* Minute tens in BCD format mask */
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#define RTC_TR_MNU_SHIFT (8) /* Minute units in BCD format shift */
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#define RTC_TR_MNU_MASK (0xf) /* Minute units in BCD format mask */
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#define RTC_TR_ST_SHIFT (4) /* Second tens in BCD format shift */
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#define RTC_TR_ST_MASK (0x7) /* Second tens in BCD format mask */
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#define RTC_TR_SU_SHIFT (0) /* Second units in BCD format shift */
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#define RTC_TR_SU_MASK (0xf) /* Second units in BCD format mask */
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/* RTC date register (RTC_DR) ----------------------------------- */
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/* Note: Bits [31:24] and [7:6] are reserved, and must be kept at reset value.
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*/
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#define RTC_DR_YT_SHIFT (20) /* Year tens in BCD format shift */
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#define RTC_DR_YT_MASK (0xf) /* Year tens in BCD format mask */
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#define RTC_DR_YU_SHIFT (16) /* Year units in BCD format shift */
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#define RTC_DR_YU_MASK (0xf) /* Year units in BCD format mask */
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#define RTC_DR_WDU_SHIFT (13) /* Weekday units shift */
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#define RTC_DR_WDU_MASK (0x7) /* Weekday units mask */
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#define RTC_DR_MT (1<<12) /* Month tens in BCD format shift */
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#define RTC_DR_MT_SHIFT (12) /* Month tens in BCD format mask */
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#define RTC_DR_MU_SHIFT (8) /* Month units in BCD format shift */
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#define RTC_DR_MU_MASK (0xf) /* Month units in BCD format mask */
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#define RTC_DR_DT_SHIFT (4) /* Date tens in BCD format shift */
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#define RTC_DR_DT_MASK (0x3) /* Date tens in BCD format mask */
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#define RTC_DR_DU_SHIFT (0) /* Date units in BCD format shift */
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#define RTC_DR_DU_MASK (0xf) /* Date units in BCD format mask */
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/* RTC control register (RTC_CR) -------------------------------- */
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/* Note: Bits [31:24] are reserved, and must be kept at reset value. */
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/* Note: Bits 7, 6 and 4 of this register can be written in initialization mode
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* only (RTC_ISR/INITF = 1).
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*/
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/* Note: Bits 2 to 0 of this register can be written only when RTC_CR WUTE bit
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* = 0 and RTC_ISR WUTWF bit = 1.
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*/
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#define RTC_CR_COE (1<<23) /* RTC_CR_COE: Calibration output enable */
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/* RTC_CR_OSEL: Output selection values */
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/* Note: These bits are used to select the flag to be routed to AFO_ALARM RTC
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* output
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*/
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#define RTC_CR_OSEL_SHIFT 21
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#define RTC_CR_OSEL_MASK (0x3)
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#define RTC_CR_OSEL_DISABLED (0x0)
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#define RTC_CR_OSEL_ALARMA (0x1)
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#define RTC_CR_OSEL_ALARMB (0x2)
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#define RTC_CR_OSEL_WAKEUP (0x3)
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#define RTC_CR_POL (1<<20) /* RTC_CR_POL: Output polarity */
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#define RTC_CR_COSEL (1<<19) /* RTC_CR_COSEL: Calibration output
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selection */
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#define RTC_CR_BKP (1<<18) /* RTC_CR_BKP: Backup */
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#define RTC_CR_SUB1H (1<<17) /* RTC_CR_SUB1H: Subtract 1 hour
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(winter time change) */
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#define RTC_CR_ADD1H (1<<16) /* RTC_CR_ADD1H: Add 1 hour (summer
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time change) */
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#define RTC_CR_TSIE (1<<15) /* RTC_CR_TSIE: Timestamp interrupt
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enable */
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#define RTC_CR_WUTIE (1<<14) /* RTC_CR_WUTIE: Wakeup timer
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interrupt enable */
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#define RTC_CR_ALRBIE (1<<13) /* RTC_CR_ALRBIE: Alarm B interrupt
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enable */
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#define RTC_CR_ALRAIE (1<<12) /* RTC_CR_ALRAIE: Alarm A interrupt
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enable */
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#define RTC_CR_TSE (1<<11) /* RTC_CR_TSE: Time stamp enable */
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#define RTC_CR_WUTE (1<<10) /* RTC_CR_WUTE: Wakeup timer enable */
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#define RTC_CR_ALRBE (1<<9) /* RTC_CR_ALRBIE: Alarm B enable */
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#define RTC_CR_ALRAE (1<<8) /* RTC_CR_ALRAE: Alarm A enable */
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#define RTC_CR_DCE (1<<7) /* RTC_CR_DCE: Course digital
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calibration enable */
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#define RTC_CR_FMT (1<<6) /* RTC_CR_FMT: Hour format */
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#define RTC_CR_BYPSHAD (1<<5) /* RTC_CR_BYPSHAD: Bypass the shadow
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registers */
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#define RTC_CR_REFCKON (1<<4) /* RTC_CR_REFCKON: Reference clock
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detection enable */
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#define RTC_CR_TSEDGE (1<<3) /* RTC_CR_TSEDGE: Timestamp event
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active edge */
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/* RTC_CR_WUCKSEL: Wakeup clock selection */
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#define RTC_CR_WUCLKSEL_SHIFT (0)
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#define RTC_CR_WUCLKSEL_MASK (0x7)
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#define RTC_CR_WUCLKSEL_RTC_DIV16 (0x0)
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#define RTC_CR_WUCLKSEL_RTC_DIV8 (0x1)
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#define RTC_CR_WUCLKSEL_RTC_DIV4 (0x2)
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#define RTC_CR_WUCLKSEL_RTC_DIV2 (0x3)
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#define RTC_CR_WUCLKSEL_SPRE (0x4)
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#define RTC_CR_WUCLKSEL_SPRE_216 (0x6)
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/* RTC initialization and status register (RTC_ISR) ------------- */
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/* Note: Bits [31:17] and [15] are reserved, and must be kept at reset value. */
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/* Note: This register is write protected (except for RTC_ISR[13:8] bits). */
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#define RTC_ISR_RECALPF (1<<16) /* RECALPF: Recalib pending flag */
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#define RTC_ISR_TAMP3F (1<<15) /* TAMP3F: TAMPER3 detection flag
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(not on F4)*/
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#define RTC_ISR_TAMP2F (1<<14) /* TAMP2F: TAMPER2 detection flag */
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#define RTC_ISR_TAMP1F (1<<13) /* TAMP1F: TAMPER detection flag */
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#define RTC_ISR_TSOVF (1<<12) /* TSOVF: Timestamp overflow flag */
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#define RTC_ISR_TSF (1<<11) /* TSF: Timestamp flag */
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#define RTC_ISR_WUTF (1<<10) /* WUTF: Wakeup timer flag */
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#define RTC_ISR_ALRBF (1<<9) /* ALRBF: Alarm B flag */
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#define RTC_ISR_ALRAF (1<<8) /* ALRAF: Alarm A flag */
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#define RTC_ISR_INIT (1<<7) /* INIT: Initialization mode */
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#define RTC_ISR_INITF (1<<6) /* INITF: Initialization flag */
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#define RTC_ISR_RSF (1<<5) /* RSF: Registers sync flag */
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#define RTC_ISR_INITS (1<<4) /* INITS: Init status flag */
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#define RTC_ISR_SHPF (1<<3) /* SHPF: Shift operation pending */
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#define RTC_ISR_WUTWF (1<<2) /* WUTWF: Wakeup timer write flag */
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#define RTC_ISR_ALRBWF (1<<1) /* ALRBWF: Alarm B write flag */
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#define RTC_ISR_ALRAWF (1<<0) /* ALRAWF: Alarm A write flag */
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/* RTC prescaler register (RTC_PRER) ---------------------------- */
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#define RTC_PRER_PREDIV_A_SHIFT (16) /* Async prescaler factor shift */
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#define RTC_PRER_PREDIV_A_MASK (0x7f) /* Async prescaler factor mask */
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#define RTC_PRER_PREDIV_S_SHIFT (0) /* Sync prescaler factor shift */
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#define RTC_PRER_PREDIV_S_MASK (0x7fff) /* Sync prescaler factor mask */
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/* RTC calibration register (RTC_CALIBR) ------------------------ */
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/* FIXME - TODO */
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/* RTC Alarm register ------------------------------------------- */
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/* Note: Applies to RTC_ALRMAR and RTC_ALRMBR */
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#define RTC_ALRMXR_MSK4 (1<<31)
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#define RTC_ALRMXR_WDSEL (1<<30)
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#define RTC_ALRMXR_DT_SHIFT (28)
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#define RTC_ALRMXR_DT_MASK (0x3)
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#define RTC_ALRMXR_DU_SHIFT (24)
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#define RTC_ALRMXR_DU_MASK (0xf)
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#define RTC_ALRMXR_MSK3 (1<<23)
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#define RTC_ALRMXR_PM (1<<22)
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#define RTC_ALRMXR_HT_SHIFT (20)
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#define RTC_ALRMXR_HT_MASK (0x3)
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#define RTC_ALRMXR_HU_SHIFT (16)
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#define RTC_ALRMXR_HU_MASK (0xf)
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#define RTC_ALRMXR_MSK2 (1<<15)
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#define RTC_ALRMXR_MNT_SHIFT (12)
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#define RTC_ALRMXR_MNT_MASK (0x7)
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#define RTC_ALRMXR_MNU_SHIFT (8)
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#define RTC_ALRMXR_MNU_MASK (0xf)
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#define RTC_ALRMXR_MSK1 (1<<7)
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#define RTC_ALRMXR_ST_SHIFT (4)
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#define RTC_ALRMXR_ST_MASK (0x7)
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#define RTC_ALRMXR_SU_SHIFT (0)
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#define RTC_ALRMXR_SU_MASK (0xf)
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/* RTC shift control register (RTC_SHIFTR) */
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/* FIXME - TODO */
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/* RTC time stamp time register (RTC_TSTR) ---------------------- */
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#define RTC_TSTR_PM (1<<22)
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#define RTC_TSTR_HT_SHIFT (20)
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#define RTC_TSTR_HT_MASK (0x3)
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#define RTC_TSTR_HU_SHIFT (16)
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#define RTC_TSTR_HU_MASK (0xf)
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#define RTC_TSTR_MNT_SHIFT (12)
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#define RTC_TSTR_MNT_MASK (0x7)
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#define RTC_TSTR_MNU_SHIFT (8)
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#define RTC_TSTR_MNU_MASK (0xf)
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#define RTC_TSTR_ST_SHIFT (4)
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#define RTC_TSTR_ST_MASK (0x7)
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#define RTC_TSTR_SU_SHIFT (0)
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#define RTC_TSTR_SU_MASK (0xf)
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/* RTC time stamp date register (RTC_TSDR) ---------------------- */
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#define RTC_TSDR_WDU_SHIFT (13)
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#define RTC_TSDR_WDU_MASK (0x7)
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#define RTC_TSDR_MT (1<<12)
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#define RTC_TSDR_MU_SHIFT (8)
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#define RTC_TSDR_MU_MASK (0xf)
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#define RTC_TSDR_DT_SHIFT (4)
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#define RTC_TSDR_DT_MASK (0x3)
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#define RTC_TSDR_DU_SHIFT (0)
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#define RTC_TSDR_DU_MASK (0xf)
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/* RTC calibration register (RTC_CALR) -------------------------- */
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/* FIXME - TODO */
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/* RTC tamper and alternate function configuration register (RTC_TAFCR) --- */
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#define RTC_TAFCR_ALARMOUTTYPE (1<<18)
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#define RTC_TAFCR_TAMPPUDIS (1<<15)
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#define RTC_TAFCR_TAMPPRCH_SHIFT (13)
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#define RTC_TAFCR_TAMPPRCH_MASK (0x3)
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#define RTC_TAFCR_TAMPPRCH_1RTC (0x0)
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#define RTC_TAFCR_TAMPPRCH_2RTC (0x1)
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#define RTC_TAFCR_TAMPPRCH_4RTC (0x2)
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#define RTC_TAFCR_TAMPPRCH_8RTC (0x3)
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#define RTC_TAFCR_TAMPFLT_SHIFT (11)
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#define RTC_TAFCR_TAMPFLT_MASK (0x3)
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#define RTC_TAFCR_TAMPFLT_EDGE1 (0x0)
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#define RTC_TAFCR_TAMPFLT_EDGE2 (0x1)
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#define RTC_TAFCR_TAMPFLT_EDGE4 (0x2)
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#define RTC_TAFCR_TAMPFLT_EDGE8 (0x3)
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#define RTC_TAFCR_TAMPFREQ_SHIFT (8)
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#define RTC_TAFCR_TAMPFREQ_MASK (0x7)
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#define RTC_TAFCR_TAMPFREQ_RTCDIV32K (0x0)
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#define RTC_TAFCR_TAMPFREQ_RTCDIV16K (0x1)
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#define RTC_TAFCR_TAMPFREQ_RTCDIV8K (0x2)
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#define RTC_TAFCR_TAMPFREQ_RTCDIV4K (0x3)
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#define RTC_TAFCR_TAMPFREQ_RTCDIV2K (0x4)
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#define RTC_TAFCR_TAMPFREQ_RTCDIV1K (0x5)
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#define RTC_TAFCR_TAMPFREQ_RTCDIV512 (0x6)
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#define RTC_TAFCR_TAMPFREQ_RTCDIV256 (0x7)
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#define RTC_TAFCR_TAMPTS (1<<7)
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#define RTC_TAFCR_TAMP3TRG (1<<6)
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#define RTC_TAFCR_TAMP3E (1<<5)
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#define RTC_TAFCR_TAMP2TRG (1<<4)
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#define RTC_TAFCR_TAMP2E (1<<3)
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#define RTC_TAFCR_TAMPIE (1<<2)
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#define RTC_TAFCR_TAMP1TRG (1<<1)
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#define RTC_TAFCR_TAMP1E (1<<0)
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/* RTC alarm X sub second register */
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/* FIXME - TODO */
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BEGIN_DECLS
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void rtc_set_prescaler(uint32_t sync, uint32_t async);
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void rtc_wait_for_synchro(void);
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void rtc_lock(void);
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void rtc_unlock(void);
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void rtc_set_wakeup_time(uint16_t wkup_time, uint8_t rtc_cr_wucksel);
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void rtc_clear_wakeup_flag(void);
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END_DECLS
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/**@}*/
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#endif /* RTC2_H */
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/** @cond */
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#else
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#warning "rtc_common_bcd.h should not be included explicitly, only via rtc.h"
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#endif
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/** @endcond */
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