2adefd95fe
Basic memory map and system control. Originally tracked via: https://github.com/libopencm3/libopencm3/pull/946
175 lines
5.6 KiB
C
175 lines
5.6 KiB
C
/** @defgroup msp432e4_memorymap MSP432E4xx Memory Map
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*
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* @ingroup MSP432E4xx_defines
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*
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* @brief Memory map for the MSP432E4xx devices
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*
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* @version 1.0.0
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*
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* @date 22 July 2018
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
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* Copyright (C) 2018 Dmitry Rezvanov <dmitry.rezvanov@yandex.ru>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#ifndef MSP432E4_MEMORYMAP_H
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#define MSP432E4_MEMORYMAP_H
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#include <libopencm3/cm3/common.h>
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/* --- MSP432E4xx specific peripheral definitions --------------------------- */
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/** System Control Base Address */
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#define SYSCTL_BASE (0x400FE000U)
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/** Hibernation Module Base Address */
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#define HIB_BASE (0x400FC000U)
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/** Flash Controller Base Address */
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#define FLASH_CTRL_BASE (0x400FD000U)
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/** EEPROM Controller Base Address */
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#define EEPROM_BASE (0x400AF000U)
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/** Micro Direct Memory Access Base Address */
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#define DMA_BASE (0x400FF000U)
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/** Advance Encryption Standard Accelerator Base Address */
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#define AES_BASE (0x44036000U)
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/** Analog-to-Digital Converter Base Address */
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#define ADC0_BASE (0x40038000U)
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#define ADC1_BASE (0x40039000U)
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/** Controller Area Network Base Address */
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#define CAN0_BASE (0x40040000U)
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#define CAN1_BASE (0x40041000U)
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/** Analog Comparator Base Address */
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#define ACMP_BASE (0x4003C000U)
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/** Cyclical Redundancy Check Base Address */
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#define CRC_BASE (0x44030000U)
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/** Data Encryption Standard Accelerator Base Address */
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#define DES_BASE (0x44038000U)
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/** Ethernet Controller Base Address */
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#define EMAC_BASE (0x400EC000U)
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/** External Peripheral Interface Base Address */
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#define EPI0_BASE (0x400D0000U)
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/** General-Purpose Input/Outputs Base Address */
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#define GPIOA_APB_BASE (0x40004000U)
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#define GPIOB_APB_BASE (0x40005000U)
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#define GPIOC_APB_BASE (0x40006000U)
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#define GPIOD_APB_BASE (0x40007000U)
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#define GPIOE_APB_BASE (0x40024000U)
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#define GPIOF_APB_BASE (0x40025000U)
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#define GPIOG_APB_BASE (0x40026000U)
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#define GPIOH_APB_BASE (0x40027000U)
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#define GPIOJ_APB_BASE (0x4003D000U)
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/** General-Purpose Input/Outputs (AHB) Base Address */
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#define GPIOA_BASE (0x40058000U)
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#define GPIOB_BASE (0x40059000U)
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#define GPIOC_BASE (0x4005A000U)
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#define GPIOD_BASE (0x4005B000U)
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#define GPIOE_BASE (0x4005C000U)
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#define GPIOF_BASE (0x4005D000U)
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#define GPIOG_BASE (0x4005E000U)
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#define GPIOH_BASE (0x4005F000U)
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#define GPIOJ_BASE (0x40060000U)
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#define GPIOK_BASE (0x40061000U)
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#define GPIOL_BASE (0x40062000U)
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#define GPIOM_BASE (0x40063000U)
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#define GPION_BASE (0x40064000U)
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#define GPIOP_BASE (0x40065000U)
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#define GPIOQ_BASE (0x40066000U)
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/** General-Purpose Timers Base Address */
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#define TIM0_BASE (0x40030000U)
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#define TIM1_BASE (0x40031000U)
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#define TIM2_BASE (0x40032000U)
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#define TIM3_BASE (0x40033000U)
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#define TIM4_BASE (0x40034000U)
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#define TIM5_BASE (0x40035000U)
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#define TIM6_BASE (0x400E0000U)
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#define TIM7_BASE (0x400E1000U)
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/** Inter-Integrated Circuit Base Address */
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#define I2C0_BASE (0x40020000U)
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#define I2C1_BASE (0x40021000U)
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#define I2C2_BASE (0x40022000U)
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#define I2C3_BASE (0x40023000U)
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#define I2C4_BASE (0x400C0000U)
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#define I2C5_BASE (0x400C1000U)
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#define I2C6_BASE (0x400C2000U)
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#define I2C7_BASE (0x400C3000U)
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#define I2C8_BASE (0x400B8000U)
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#define I2C9_BASE (0x400B9000U)
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/** LCD Controller Base Address */
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#define LCD_BASE (0x44050000U)
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/** Pulse Width Modulator Base Address */
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#define PWM0_BASE (0x40028000U)
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/** 1-Wire Master Module Base Address */
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#define ONEWIRE_BASE (0x400B6000U)
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/** Quad Synchronous Serial Interface Base Address */
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#define SSI0_BASE (0x40008000U)
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#define SSI1_BASE (0x40009000U)
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#define SSI2_BASE (0x4000A000U)
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#define SSI3_BASE (0x4000B000U)
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/** Quadrature Encoder Interface Base Address */
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#define QEI0_BASE (0x4002C000U)
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/** SHA/MD5 Accelerator Base Address */
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#define SHA_BASE (0x44034000U)
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/** Universal Asynchronous Receiver/Transmitter Base Address */
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#define UART0_BASE (0x4000C000U)
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#define UART1_BASE (0x4000D000U)
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#define UART2_BASE (0x4000E000U)
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#define UART3_BASE (0x4000F000U)
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#define UART4_BASE (0x40010000U)
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#define UART5_BASE (0x40011000U)
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#define UART6_BASE (0x40012000U)
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#define UART7_BASE (0x40013000U)
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/** Universal Serial Bus Controller Base Address */
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#define USB_BASE (0x40050000U)
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/** Watchdog Timers Base Address */
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#define WDT0_BASE (0x40000000U)
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#define WDT1_BASE (0x40001000U)
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#endif /* MSP432E4_MEMORYMAP_H */
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/**@}*/
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