2b1ddc8490
The original submitter of this squished everything into one series, and has not returned. The code mostly appears good, and review comments were followed for the most part. The project doesn't really maintain any testing or board farm for sam3/sam4 parts, so we're going to just trust our users. Reviewed-by: Karl Palsson <karlp@tweak.net.au> sam/4l: IRQ Configuration file (irq.json) sam/4l: Basic Memory Map. sam/4l: GPIO Defines. sam/4l: GPIO Functions Added everything that needed to compile the library: Makefile, Linker Script and common includes. sam/4l: SCIF function to start OSC. sam/4l: GPIO Enable/Disable and Multiplexing configuration functions. sam/4l: PLL Clock configuration. sam/4l: Peripheral clock configuration and basic USART support. sam: USART Character length configuration. sam/4l: Generic Clock configuration functions. sam/4l: Analog to Digital Converter Interface (ADCIFE) basic support.
329 lines
10 KiB
C
329 lines
10 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_SCIF_H
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#define LIBOPENCM3_SCIF_H
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/sam/memorymap.h>
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/* ------------ SCIF Registers ------------------------------ */
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/* Interrupt Enable Register IER Write Only */
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#define SCIF_IER MMIO32(SCIF_BASE)
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/* Interrupt Disable Register IDR Write Only */
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#define SCIF_IDR MMIO32(SCIF_BASE + 0x0004)
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/* Interrupt Mask Register IMR Read Only */
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#define SCIF_IMR MMIO32(SCIF_BASE + 0x0008)
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/* Interrupt Status Register ISR Read Only */
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#define SCIF_ISR MMIO32(SCIF_BASE + 0x000C)
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/* Interrupt Clear Register ICR Write Only */
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#define SCIF_ICR MMIO32(SCIF_BASE + 0x0010)
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/* Power and Clocks Status Register PCLKSR Read Only */
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#define SCIF_PCLKSR MMIO32(SCIF_BASE + 0x0014)
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/* Unlock Register UNLOCK Write Only */
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#define SCIF_UNLOCK MMIO32(SCIF_BASE + 0x0018)
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#define SCIF_UNLOCK_KEY (0xaa << 24)
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/* Chip Specific Configuration Register CSCR Read/Write */
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#define SCIF_CSCR MMIO32(SCIF_BASE + 0x001C)
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/* Oscillator Control Register OSCCTRL0 Read/Write */
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#define SCIF_OSCCTRL0 MMIO32(SCIF_BASE + 0x0020)
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#define SCIF_OSCCTRL0_KEY (SCIF_UNLOCK_KEY | 0x0020)
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/* PLL0 Control Register PLL0 Read/Write */
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#define SCIF_PLL0 MMIO32(SCIF_BASE + 0x0024)
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#define SCIF_PLL0_KEY (SCIF_UNLOCK_KEY | 0x0024)
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/* DFLL0 Config Register DFLL0CONF Read/Write */
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#define SCIF_DFLL0CONF MMIO32(SCIF_BASE + 0x0028)
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/* DFLL Value Register DFLL0VAL Read/Write */
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#define SCIF_DFLL0VAL MMIO32(SCIF_BASE + 0x002C)
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/* DFLL0 Multiplier Register DFLL0MUL Read/Write */
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#define SCIF_DFLL0MUL MMIO32(SCIF_BASE + 0x0030)
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/* DFLL0 Step Register DFLL0STEP Read/Write */
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#define SCIF_DFLL0STEP MMIO32(SCIF_BASE + 0x0034)
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/* DFLL0 Spread Spectrum Generator Control Register DFLL0SSG Read/Write */
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#define SCIF_DFLL0SSG MMIO32(SCIF_BASE + 0x0038)
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/* DFLL0 Ratio Register DFLL0RATIO Read Only */
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#define SCIF_DFLL0RATIO MMIO32(SCIF_BASE + 0x003C)
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/* DFLL0 Synchronization Register DFLL0SYNC Write Only */
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#define SCIF_DFLL0SYNC MMIO32(SCIF_BASE + 0x0040)
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/* System RC Oscillator Calibration Register RCCR Read/Write */
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#define SCIF_RCCR MMIO32(SCIF_BASE + 0x0044)
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/* 4/8/12MHz RC Oscillator Configuration Register RCFASTCFG Read/Write */
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#define SCIF_RCFASTCFG MMIO32(SCIF_BASE + 0x0048)
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/* 4/8/12MHz RC Oscillator Status Register RCFASTSR Read Only */
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#define SCIF_RCFASTSR MMIO32(SCIF_BASE + 0x004C)
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/* 80MHz RC Oscillator Register RC80MCR Read/Write */
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#define SCIF_RC80MCR MMIO32(SCIF_BASE + 0x0050)
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/* High Resolution Prescaler Control Register HRPCR Read/Write */
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#define SCIF_HPPCR MMIO32(SCIF_BASE + 0x0064)
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/* Fractional Prescaler Control Register FPCR Read/Write */
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#define SCIF_FPCR MMIO32(SCIF_BASE + 0x0068)
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/* Fractional Prescaler Multiplier Register FPMUL Read/Write */
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#define SCIF_FPMUL MMIO32(SCIF_BASE + 0x006C)
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/* Fractional Prescaler DIVIDER Register FPDIV Read/Write */
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#define SCIF_FPDIV MMIO32(SCIF_BASE + 0x006C)
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/* Generic Clock Control1 GCCTRL0 Read/Write */
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#define SCIF_GCCTRL0 MMIO32(SCIF_BASE + 0x0074)
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/* Generic Clock Control1 GCCTRL1 Read/Write */
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#define SCIF_GCCTRL1 MMIO32(SCIF_BASE + 0x0078)
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/* Generic Clock Control2 GCCTRL2 Read/Write */
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#define SCIF_GCCTRL2 MMIO32(SCIF_BASE + 0x007C)
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/* Generic Clock Control3 GCCTRL3 Read/Write */
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#define SCIF_GCCTRL3 MMIO32(SCIF_BASE + 0x0080)
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/* Generic Clock Control4 GCCTRL4 Read/Write */
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#define SCIF_GCCTRL4 MMIO32(SCIF_BASE + 0x0084)
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/* Generic Clock Control5 GCCTRL5 Read/Write */
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#define SCIF_GCCTRL5 MMIO32(SCIF_BASE + 0x0088)
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/* Generic Clock Control6 GCCTRL6 Read/Write */
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#define SCIF_GCCTRL6 MMIO32(SCIF_BASE + 0x008C)
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/* Generic Clock Control7 GCCTRL7 Read/Write */
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#define SCIF_GCCTRL7 MMIO32(SCIF_BASE + 0x0090)
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/* Generic Clock Control8 GCCTRL8 Read/Write */
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#define SCIF_GCCTRL8 MMIO32(SCIF_BASE + 0x0094)
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/* Generic Clock Control9 GCCTRL9 Read/Write */
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#define SCIF_GCCTRL9 MMIO32(SCIF_BASE + 0x0098)
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/* Generic Clock Control10 GCCTRL10 Read/Write */
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#define SCIF_GCCTRL10 MMIO32(SCIF_BASE + 0x009C)
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/* Generic Clock Control11 GCCTRL11 Read/Write */
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#define SCIF_GCCTRL11 MMIO32(SCIF_BASE + 0x00A0)
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#define SCIF_GCTRL(N) MMIO32(SCIF_BASE + 0x0074 + 0x0004 * (N))
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#define SCIF_GCLK_MAX_NUM 11
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/* 4/8/12MHz RC Oscillator Version Register RCFASTVERSION Read-only */
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#define SCIF_RCFASTVERSION MMIO32(SCIF_BASE + 0x03D8)
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/* Generic Clock Prescaler Version Register GCLKPRESCVERSION Read-only */
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#define SCIF_GCLKPRESCVERSION MMIO32(SCIF_BASE + 0x03DC)
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/* PLL Version Register PLLIFAVERSION Read-only */
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#define SCIF_PLLIFAVERSION MMIO32(SCIF_BASE + 0x03E0)
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/* Oscillator0 Version Register OSCIFAVERSION Read-only */
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#define SCIF_OSCIFAVERSION MMIO32(SCIF_BASE + 0x03E4)
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/* DFLL Version Register DFLLIFBVERSION Read-only */
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#define SCIF_DFLLIFBVERSION MMIO32(SCIF_BASE + 0x03E8)
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/* System RC Oscillator Version Register RCOSCIFAVERSION Read-only */
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#define SCIF_RCOSCIFAVERSION MMIO32(SCIF_BASE + 0x03EC)
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/* 80MHz RC Oscillator Version Register RC80MVERSION Read-only */
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#define SCIF_RC80MVERSION MMIO32(SCIF_BASE + 0x03F4)
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/* Generic Clock Version Register GCLKVERSION Read-only */
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#define SCIF_GCLKVERSION MMIO32(SCIF_BASE + 0x03F8)
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/* SCIF Version Register VERSION Read-Only */
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#define SCIF_VERSION MMIO32(SCIF_BASE + 0x03FC)
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/* ---------------- SCIF Registers' Contents ------------------- */
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/* Interrupt Enable/Disable/Mask/Status/Clear registers and PCLKSR
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* have the same bit configuration */
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#define SCIF_OSC0RDY (1 << 0)
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#define SCIF_DFLL0LOCKC (1 << 1)
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#define SCIF_DFLL0LOCKF (1 << 2)
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#define SCIF_DFLL0RDY (1 << 3)
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#define SCIF_DFLL0RCS (1 << 4)
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#define SCIF_PLL0LOCK (1 << 6)
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#define SCIF_PLL0LOCKLOST (1 << 7)
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#define SCIF_RCFASTLOCK (1 << 13)
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#define SCIF_RCFASTLOCKLOST (1 << 14)
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#define SCIF_OSCCTRL_MODE (1 << 0)
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#define SCIF_OSCCTRL_GAIN_SHIFT 1
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#define SCIF_OSCCTRL_GAIN_MASK (3 << SCIF_OSCCTRL_GAIN_SHIFT)
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#define SCIF_OSCCTRL_AGC (1 << 3)
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#define SCIF_OSCCTRL_STARTUP_SHIFT 8
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#define SCIF_OSCCTRL_STARTUP_MASK (0xf << SCIF_OSCCTRL_STARTUP_SHIFT)
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#define SCIF_OSCCTRL_OSCEN (1 << 16)
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#define _MASKED_VALUE(V, S, M) (((V) << (S)) & (M))
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#define SCIF_PLL0_PLLEN (1 << 0)
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#define SCIF_PLL0_PLLOSC_SHIFT 1
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#define SCIF_PLL0_PLLOSC_MASK (3 << SCIF_PLL0_PLLOSC_SHIFT)
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#define SCIF_PLL0_PLLOSC_MASKED(V) _MASKED_VALUE((V), SCIF_PLL0_PLLOSC_SHIFT, SCIF_PLL0_PLLOSC_MASK)
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#define SCIF_PLL0_PLLOPT_SHIFT 3
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#define SCIF_PLL0_PLLOPT_MASK (7 << SCIF_PLL0_PLLOPT_SHIFT)
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#define SCIF_PLL0_PLLOPT_MASKED(V) _MASKED_VALUE((V), SCIF_PLL0_PLLOPT_SHIFT, SCIF_PLL0_PLLOPT_MASK)
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#define SCIF_PLL0_PLLDIV_SHIFT 8
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#define SCIF_PLL0_PLLDIV_MASK (0xf << SCIF_PLL0_PLLDIV_SHIFT)
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#define SCIF_PLL0_PLLDIV_MASKED(V) _MASKED_VALUE((V), SCIF_PLL0_PLLDIV_SHIFT, SCIF_PLL0_PLLDIV_MASK)
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#define SCIF_PLL0_PLLMUL_SHIFT 16
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#define SCIF_PLL0_PLLMUL_MASK (0xf << SCIF_PLL0_PLLMUL_SHIFT)
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#define SCIF_PLL0_PLLMUL_MASKED(V) _MASKED_VALUE((V), SCIF_PLL0_PLLMUL_SHIFT, SCIF_PLL0_PLLMUL_MASK)
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#define SCIF_PLL0_PLLCOUNT_SHIFT 24
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#define SCIF_PLL0_PLLCOUNT_MASK (0x3f << SCIF_PLL0_PLLCOUNT_SHIFT)
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#define SCIF_PLL0_PLLCOUNT_MASKED(V) _MASKED_VALUE((V), SCIF_PLL0_PLLCOUNT_SHIFT, SCIF_PLL0_PLLCOUNT_MASK)
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#define SCIF_GCCTRL_CEN (1 << 0)
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#define SCIF_GCCTRL_DIVEN (1 << 1)
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#define SCIF_GCCTRL_OSCSEL_SHIFT 8
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#define SCIF_GCCTRL_OSCSEL_MASK (0x1f << SCIF_GCCTRL_OSCSEL_SHIFT)
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#define SCIF_GCCTRL_OSCSEL_MASKED(V) _MASKED_VALUE(V, SCIF_GCCTRL_OSCSEL_SHIFT, SCIF_GCCTRL_OSCSEL_MASK)
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#define SCIF_GCCTRL_DIV_SHIFT 16
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#define SCIF_GCCTRL_DIV_MASK (0xffff << SCIF_GCCTRL_DIV_SHIFT)
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#define SCIF_GCCTRL_DIV_MASKED(V) _MASKED_VALUE(V, SCIF_GCCTRL_DIV_SHIFT, SCIF_GCCTRL_DIV_MASK)
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enum osc_mode {
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OSC_MODE_XIN = 0,
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OSC_MODE_XIN_XOUT,
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};
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enum osc_startup {
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OSC_STARTUP_0 = 0,
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OSC_STARTUP_4 = 8,
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OSC_STARTUP_8 = 9,
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OSC_STARTUP_16 = 10,
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OSC_STARTUP_32 = 11,
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OSC_STARTUP_64 = 1,
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OSC_STARTUP_128 = 2,
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OSC_STARTUP_256 = 12,
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OSC_STARTUP_512 = 13,
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OSC_STARTUP_1K = 14,
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OSC_STARTUP_2K = 3,
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OSC_STARTUP_4K = 4,
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OSC_STARTUP_8K = 5,
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OSC_STARTUP_16K = 6,
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OSC_STARTUP_32K = 7,
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};
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enum pll_clk_src {
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PLL_CLK_SRC_OSC0 = 0,
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PLL_CLK_SRC_GCLK9,
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};
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/* Generic Clock Source
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* 0 RCSYS System RC oscillator clock
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* 1 OSC32K Output clock from OSC32K
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* 2 DFLL0 Output clock from DFLL0
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* 3 OSC0 Output clock from Oscillator0
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* 4 RC80M Output from 80MHz RCOSC
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* 5 RCFAST Output from 4,8,12MHz RCFAST
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* 6 RC1M Output from 1MHz RC1M
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* 7 CLK_CPU The clock the CPU runs on
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* 8 CLK_HSB High Speed Bus clock
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* 9 CLK_PBA Peripheral Bus A clock
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* 10 CLK_PBB Peripheral Bus B clock
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* 11 CLK_PBC Peripheral Bus C clock
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* 12 CLK_PBD Peripheral Bus D clock
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* 13 RC32K Output from 32kHz RCOSC
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* 14 Reserved
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* 15 CLK_1K 1kHz output clock from OSC32K
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* 16 PLL0 Output clock from PLL0
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* 17 HRP High Resolution Prescaler Output
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* 18 FP Fractionnal Prescaler Output
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* 19-20 GCLK_IN[0-1] GCLK_IN[0-1] pins, digital clock input
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* 21 GCLK11 Generic Clock 11. Can not be use as input to itself.
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*/
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enum gclk_src {
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GCLK_SRC_RCSYS,
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GCLK_SRC_OSC32K,
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GCLK_SRC_DFLL0,
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GCLK_SRC_OSC0,
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GCLK_SRC_RC80M,
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GCLK_SRC_RCFAST,
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GCLK_SRC_RC1M,
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GCLK_SRC_CLK_CPU,
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GCLK_SRC_CLK_HSB,
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GCLK_SRC_CLK_PBA,
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GCLK_SRC_CLK_PBB,
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GCLK_SRC_CLK_PBC,
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GCLK_SRC_CLK_PBD,
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GCLK_SRC_RC32K,
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GCLK_SRC_RESERVED_,
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GCLK_SRC_CLK_1K,
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GCLK_SRC_PLL0,
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GCLK_SRC_HRP,
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GCLK_SRC_FP,
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GCLK_SRC_GCLK_IN0,
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GCLK_SRC_GCLK_IN1,
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GCLK_SRC_GCLK11,
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};
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enum generic_clock {
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GENERIC_CLOCK0,
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GENERIC_CLOCK1,
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GENERIC_CLOCK2,
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GENERIC_CLOCK3,
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GENERIC_CLOCK4,
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GENERIC_CLOCK5,
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GENERIC_CLOCK6,
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GENERIC_CLOCK7,
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GENERIC_CLOCK8,
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GENERIC_CLOCK9,
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GENERIC_CLOCK10,
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GENERIC_CLOCK_ADCIFE = GENERIC_CLOCK10,
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GENERIC_CLOCK11,
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};
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BEGIN_DECLS
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int scif_osc_enable(enum osc_mode mode, uint32_t freq, enum osc_startup startup);
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int scif_enable_pll(uint8_t delay, uint8_t mul, uint8_t div, uint8_t pll_opt, enum pll_clk_src source_clock);
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void scif_enable_gclk(enum generic_clock gclk, enum gclk_src source_clock, uint16_t div);
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END_DECLS
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#endif /* LIBOPENCM3_SCIF_H */
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