502 lines
15 KiB
C
502 lines
15 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Gareth McMullin <gareth@blacksphere.co.nz>
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* Copyright (C) 2015 Felix Held <felix-libopencm3@felixheld.de>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#if defined(LIBOPENCM3_PMC_H)
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#ifndef LIBOPENCM3_PMC_COMMON_ALL_H
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#define LIBOPENCM3_PMC_COMMON_ALL_H
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#include <libopencm3/cm3/common.h>
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/* --- Power Management Controller (PMC) registers ----------------------- */
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/* System Clock Enable Register */
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#define PMC_SCER MMIO32(PMC_BASE + 0x0000)
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/* System Clock Disable Register */
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#define PMC_SCDR MMIO32(PMC_BASE + 0x0004)
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/* System Clock Status Register */
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#define PMC_SCSR MMIO32(PMC_BASE + 0x0008)
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/* Main Oscillator Register */
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#define CKGR_MOR MMIO32(PMC_BASE + 0x0020)
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/* Main Clock Frequency Register */
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#define CKGR_MCFR MMIO32(PMC_BASE + 0x0024)
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/* PLLA Register */
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#define CKGR_PLLAR MMIO32(PMC_BASE + 0x0028)
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/* Master Clock Register */
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#define PMC_MCKR MMIO32(PMC_BASE + 0x0030)
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/* Programmable Clock 0 Register */
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#define PMC_PCK0 MMIO32(PMC_BASE + 0x0040)
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/* Programmable Clock 1 Register */
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#define PMC_PCK1 MMIO32(PMC_BASE + 0x0044)
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/* Programmable Clock 2 Register */
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#define PMC_PCK2 MMIO32(PMC_BASE + 0x0048)
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/* Interrupt Enable Register */
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#define PMC_IER MMIO32(PMC_BASE + 0x0060)
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/* Interrupt Disable Register */
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#define PMC_IDR MMIO32(PMC_BASE + 0x0064)
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/* Status Register */
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#define PMC_SR MMIO32(PMC_BASE + 0x0068)
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/* Interrupt Mask Register */
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#define PMC_IMR MMIO32(PMC_BASE + 0x006C)
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/* Fast Startup Mode Register */
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#define PMC_FSMR MMIO32(PMC_BASE + 0x0070)
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/* Fast Startup Polarity Register */
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#define PMC_FSPR MMIO32(PMC_BASE + 0x0074)
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/* Fault Output Clear Register */
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#define PMC_FOCR MMIO32(PMC_BASE + 0x0078)
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/* Write Protect Mode Register */
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#define PMC_WPMR MMIO32(PMC_BASE + 0x00E4)
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/* Write Protect Status Register */
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#define PMC_WPSR MMIO32(PMC_BASE + 0x00E8)
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/* --- Register contents --------------------------------------------------- */
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/* --- PMC System Clock Enable Register (PMC_SCER) ------------------------- */
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/* Programmable Clock Output Enable */
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#define PMC_SCER_PCK0 (0x01 << 8)
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#define PMC_SCER_PCK1 (0x01 << 9)
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#define PMC_SCER_PCK2 (0x01 << 10)
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/* --- PMC System Clock Disable Register (PMC_SCDR) ------------------------ */
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/* Programmable Clock Output Disable */
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#define PMC_SCDR_PCK0 (0x01 << 8)
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#define PMC_SCDR_PCK1 (0x01 << 9)
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#define PMC_SCDR_PCK2 (0x01 << 10)
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/* --- PMC System Clock Status Register (PMC_SCSR) ------------------------- */
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/* Programmable Clock Output Status */
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#define PMC_SCSR_PCK0 (0x01 << 8)
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#define PMC_SCSR_PCK1 (0x01 << 9)
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#define PMC_SCSR_PCK2 (0x01 << 10)
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/* for bit definitions for PMC System Clock Enable/Disable/Status Register see
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* periph.h */
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/* --- PMC Clock Generator Main Oscillator Register (CKGR_MOR) ------------- */
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/* Clock Failure Detector Enable */
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#define CKGR_MOR_CFDEN (0x01 << 25)
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/* Main Oscillator Selection */
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#define CKGR_MOR_MOSCSEL (0x01 << 24)
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/* Password for changing settings */
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#define CKGR_MOR_KEY (0x37 << 16)
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/* Main Crystal Oscillator Start-up Time */
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#define CKGR_MOR_MOSCXTST_SHIFT 8
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#define CKGR_MOR_MOSCXTST_MASK (0xFF << 8)
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/* Main On-Chip RC Oscillator Frequency Selection */
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#define CKGR_MOR_MOSCRCF_SHIFT 4
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#define CKGR_MOR_MOSCRCF_MASK (0x07 << CKGR_MOR_MOSCRCF_SHIFT)
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/* Main On-Chip RC Oscillator selectable frequencies */
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#define CKGR_MOR_MOSCRCF_4MHZ (0 << CKGR_MOR_MOSCRCF_SHIFT)
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#define CKGR_MOR_MOSCRCF_8MHZ (1 << CKGR_MOR_MOSCRCF_SHIFT)
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#define CKGR_MOR_MOSCRCF_12MHZ (2 << CKGR_MOR_MOSCRCF_SHIFT)
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/* Main On-Chip RC Oscillator Enable */
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#define CKGR_MOR_MOSCRCEN (0x01 << 3)
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/* Main Crystal Oscillator Bypass */
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#define CKGR_MOR_MOSCXTBY (0x01 << 1)
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/* Main Crystal Oscillator Enable */
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#define CKGR_MOR_MOSCXTEN (0x01 << 0)
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/* --- PMC Clock Generator Main Clock Frequency Register (CKGR_MCFR) ------- */
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/* Main Clock Ready */
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#define CKGR_MCFR_MAINFRDY (0x01 << 16)
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/* Main Clock Frequency */
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#define CKGR_MCFR_MAINF_SHIFT 0
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#define CKGR_MCFR_MAINF_MASK (0xFFFF << CKGR_MCFR_MAINF_SHIFT)
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/* --- PMC Clock Generator PLLA Register (CKGR_PLLAR) ---------------------- */
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/* must be set to program CKGR_PLLAR */
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#define CKGR_PLLAR_ONE (0x01 << 29)
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/* PLLA Multiplier */
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#define CKGR_PLLAR_MULA_SHIFT 16
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#define CKGR_PLLAR_MULA_MASK (0x7FF << CKGR_PLLAR_MULA_SHIFT)
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/* PLLA Counter */
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#define CKGR_PLLAR_PLLACOUNT_SHIFT 8
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#define CKGR_PLLAR_PLLACOUNT_MASK (0x3F << CKGR_PLLAR_PLLACOUNT_SHIFT)
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/* Divider */
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#define CKGR_PLLAR_DIVA_SHIFT 0
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#define CKGR_PLLAR_DIVA_MASK (0xFF << CKGR_PLLAR_DIVA_SHIFT)
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/* --- PMC Master Clock Register (PMC_MCKR) -------------------------------- */
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/* Processor Clock Prescaler */
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#define PMC_MCKR_PRES_SHIFT 4
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#define PMC_MCKR_PRES_MASK (0x07 << PMC_MCKR_PRES_SHIFT)
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#define PMC_MCKR_PRES_CLK_1 (0 << PMC_MCKR_PRES_SHIFT)
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#define PMC_MCKR_PRES_CLK_2 (1 << PMC_MCKR_PRES_SHIFT)
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#define PMC_MCKR_PRES_CLK_4 (2 << PMC_MCKR_PRES_SHIFT)
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#define PMC_MCKR_PRES_CLK_8 (3 << PMC_MCKR_PRES_SHIFT)
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#define PMC_MCKR_PRES_CLK_16 (4 << PMC_MCKR_PRES_SHIFT)
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#define PMC_MCKR_PRES_CLK_32 (5 << PMC_MCKR_PRES_SHIFT)
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#define PMC_MCKR_PRES_CLK_64 (6 << PMC_MCKR_PRES_SHIFT)
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#define PMC_MCKR_PRES_CLK_3 (7 << PMC_MCKR_PRES_SHIFT)
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/* Master Clock Source Selection */
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#define PMC_MCKR_CSS_SHIFT 0
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#define PMC_MCKR_CSS_MASK (0x03 << PMC_MCKR_CSS_SHIFT)
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#define PMC_MCKR_CSS_SLOW_CLK (0 << PMC_MCKR_CSS_SHIFT)
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#define PMC_MCKR_CSS_MAIN_CLK (1 << PMC_MCKR_CSS_SHIFT)
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#define PMC_MCKR_CSS_PLLA_CLK (2 << PMC_MCKR_CSS_SHIFT)
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/* --- PMC Programmable Clock Register 0 (PMC_PCK0) ------------------------ */
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/* Programmable Clock Prescaler */
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#define PMC_PCK0_PRES_SHIFT 4
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#define PMC_PCK0_PRES_MASK (0x07 << PMC_PCK0_PRES_SHIFT)
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#define PMC_PCK0_PRES_CLK_1 (0 << PMC_PCK0_PRES_SHIFT)
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#define PMC_PCK0_PRES_CLK_2 (1 << PMC_PCK0_PRES_SHIFT)
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#define PMC_PCK0_PRES_CLK_4 (2 << PMC_PCK0_PRES_SHIFT)
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#define PMC_PCK0_PRES_CLK_8 (3 << PMC_PCK0_PRES_SHIFT)
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#define PMC_PCK0_PRES_CLK_16 (4 << PMC_PCK0_PRES_SHIFT)
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#define PMC_PCK0_PRES_CLK_32 (5 << PMC_PCK0_PRES_SHIFT)
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#define PMC_PCK0_PRES_CLK_64 (6 << PMC_PCK0_PRES_SHIFT)
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/* Master Clock Source Selection */
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#define PMC_PCK0_CSS_SHIFT 0
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#define PMC_PCK0_CSS_MASK (0x07 << PMC_PCK0_CSS_SHIFT)
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#define PMC_PCK0_CSS_SLOW_CLK (0 << PMC_PCK0_CSS_SHIFT)
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#define PMC_PCK0_CSS_MAIN_CLK (1 << PMC_PCK0_CSS_SHIFT)
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#define PMC_PCK0_CSS_PLLA_CLK (2 << PMC_PCK0_CSS_SHIFT)
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#define PMC_PCK0_CSS_MCK (4 << PMC_PCK0_CSS_SHIFT)
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/* --- PMC Programmable Clock Register 1 (PMC_PCK1) ------------------------ */
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/* Programmable Clock Prescaler */
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#define PMC_PCK1_PRES_SHIFT 4
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#define PMC_PCK1_PRES_MASK (0x07 << PMC_PCK1_PRES_SHIFT)
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#define PMC_PCK1_PRES_CLK_1 (0 << PMC_PCK1_PRES_SHIFT)
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#define PMC_PCK1_PRES_CLK_2 (1 << PMC_PCK1_PRES_SHIFT)
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#define PMC_PCK1_PRES_CLK_4 (2 << PMC_PCK1_PRES_SHIFT)
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#define PMC_PCK1_PRES_CLK_8 (3 << PMC_PCK1_PRES_SHIFT)
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#define PMC_PCK1_PRES_CLK_16 (4 << PMC_PCK1_PRES_SHIFT)
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#define PMC_PCK1_PRES_CLK_32 (5 << PMC_PCK1_PRES_SHIFT)
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#define PMC_PCK1_PRES_CLK_64 (6 << PMC_PCK1_PRES_SHIFT)
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/* Master Clock Source Selection */
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#define PMC_PCK1_CSS_SHIFT 0
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#define PMC_PCK1_CSS_MASK (0x07 << PMC_PCK1_CSS_SHIFT)
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#define PMC_PCK1_CSS_SLOW_CLK (0 << PMC_PCK1_CSS_SHIFT)
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#define PMC_PCK1_CSS_MAIN_CLK (1 << PMC_PCK1_CSS_SHIFT)
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#define PMC_PCK1_CSS_PLLA_CLK (2 << PMC_PCK1_CSS_SHIFT)
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#define PMC_PCK1_CSS_MCK (4 << PMC_PCK1_CSS_SHIFT)
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/* --- PMC Programmable Clock Register 2 (PMC_PCK2) ------------------------ */
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/* Programmable Clock Prescaler */
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#define PMC_PCK2_PRES_SHIFT 4
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#define PMC_PCK2_PRES_MASK (0x07 << PMC_PCK2_PRES_SHIFT)
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#define PMC_PCK2_PRES_CLK_1 (0 << PMC_PCK2_PRES_SHIFT)
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#define PMC_PCK2_PRES_CLK_2 (1 << PMC_PCK2_PRES_SHIFT)
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#define PMC_PCK2_PRES_CLK_4 (2 << PMC_PCK2_PRES_SHIFT)
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#define PMC_PCK2_PRES_CLK_8 (3 << PMC_PCK2_PRES_SHIFT)
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#define PMC_PCK2_PRES_CLK_16 (4 << PMC_PCK2_PRES_SHIFT)
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#define PMC_PCK2_PRES_CLK_32 (5 << PMC_PCK2_PRES_SHIFT)
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#define PMC_PCK2_PRES_CLK_64 (6 << PMC_PCK2_PRES_SHIFT)
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/* Master Clock Source Selection */
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#define PMC_PCK2_CSS_SHIFT 0
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#define PMC_PCK2_CSS_MASK (0x07 << PMC_PCK2_CSS_SHIFT)
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#define PMC_PCK2_CSS_SLOW_CLK (0 << PMC_PCK2_CSS_SHIFT)
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#define PMC_PCK2_CSS_MAIN_CLK (1 << PMC_PCK2_CSS_SHIFT)
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#define PMC_PCK2_CSS_PLLA_CLK (2 << PMC_PCK2_CSS_SHIFT)
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#define PMC_PCK2_CSS_MCK (4 << PMC_PCK2_CSS_SHIFT)
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/* --- PMC Interrupt Enable Register (PMC_IER) ----------------------------- */
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/* Clock Failure Detector Event Interrupt Enable */
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#define PMC_IER_CFDEV (0x01 << 18)
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/* Main On-Chip RC Status Interrupt Enable */
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#define PMC_IER_MOSCRCS (0x01 << 17)
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/* Main Oscillator Selection Status Interrupt Enable */
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#define PMC_IER_MOSCSELS (0x01 << 16)
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/* Programmable Clock Ready 2 Interrupt Enable */
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#define PMC_IER_PCKRDY2 (0x01 << 10)
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/* Programmable Clock Ready 1 Interrupt Enable */
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#define PMC_IER_PCKRDY1 (0x01 << 9)
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/* Programmable Clock Ready 0 Interrupt Enable */
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#define PMC_IER_PCKRDY0 (0x01 << 8)
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/* Master Clock Ready Interrupt Enable */
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#define PMC_IER_MCKRDY (0x01 << 3)
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/* PLLA Lock Interrupt Enable */
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#define PMC_IER_LOCKA (0x01 << 1)
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/* Main Crystal Oscillator Status Interrupt Enable */
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#define PMC_IER_MOSCXTS (0x01 << 0)
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/* --- PMC Interrupt Disable Register (PMC_IDR) ----------------------------- */
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/* Clock Failure Detector Event Interrupt Disable */
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#define PMC_IDR_CFDEV (0x01 << 18)
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/* Main On-Chip RC Status Interrupt Disable */
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#define PMC_IDR_MOSCRCS (0x01 << 17)
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/* Main Oscillator Selection Status Interrupt Disable */
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#define PMC_IDR_MOSCSELS (0x01 << 16)
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/* Programmable Clock Ready 2 Interrupt Disable */
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#define PMC_IDR_PCKRDY2 (0x01 << 10)
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/* Programmable Clock Ready 1 Interrupt Disable */
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#define PMC_IDR_PCKRDY1 (0x01 << 9)
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/* Programmable Clock Ready 0 Interrupt Disable */
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#define PMC_IDR_PCKRDY0 (0x01 << 8)
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/* Master Clock Ready Interrupt Disable */
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#define PMC_IDR_MCKRDY (0x01 << 3)
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/* PLLA Lock Interrupt Disable */
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#define PMC_IDR_LOCKA (0x01 << 1)
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/* Main Crystal Oscillator Status Interrupt Disable */
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#define PMC_IDR_MOSCXTS (0x01 << 0)
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/* --- PMC Status Register (PMC_SR) ---------------------------------------- */
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/* Clock Failure Detector Fault Output Status */
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#define PMC_SR_FOS (0x01 << 20)
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/* Clock Failure Detector Status */
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#define PMC_SR_CFDS (0x01 << 19)
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/* Clock Failure Detector Event */
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#define PMC_SR_CFDEV (0x01 << 18)
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/* Main On-Chip RC Oscillator Status */
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#define PMC_SR_MOSCRCS (0x01 << 17)
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/* Main Oscillator Selection Status */
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#define PMC_SR_MOSCSELS (0x01 << 16)
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/* Programmable Clock 2 Ready Status */
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#define PMC_SR_PCKRDY2 (0x01 << 10)
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/* Programmable Clock 1 Ready Status */
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#define PMC_SR_PCKRDY1 (0x01 << 9)
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/* Programmable Clock 0 Ready Status */
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#define PMC_SR_PCKRDY0 (0x01 << 8)
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/* Slow Clock Oscillator Selection */
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#define PMC_SR_OSCSELS (0x01 << 7)
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/* Master Clock Status */
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#define PMC_SR_MCKRDY (0x01 << 3)
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/* PLLA Lock Status */
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#define PMC_SR_LOCKA (0x01 << 1)
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/* Main XTAL Oscillator Status */
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#define PMC_SR_MOSCXTS (0x01 << 0)
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/* --- PMC Interrupt Mask Register (PMC_IMR) ------------------------------- */
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/* Clock Failure Detector Event Interrupt Mask */
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#define PMC_IMR_CFDEV (0x01 << 18)
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/* Main On-Chip RC Status Interrupt Mask */
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#define PMC_IMR_MOSCRCS (0x01 << 17)
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/* Main Oscillator Selection Status Interrupt Mask */
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#define PMC_IMR_MOSCSELS (0x01 << 16)
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/* Programmable Clock Ready 2 Interrupt Mask */
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#define PMC_IMR_PCKRDY2 (0x01 << 10)
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/* Programmable Clock Ready 1 Interrupt Mask */
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#define PMC_IMR_PCKRDY1 (0x01 << 9)
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/* Programmable Clock Ready 0 Interrupt Mask */
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#define PMC_IMR_PCKRDY0 (0x01 << 8)
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/* Master Clock Ready Interrupt Mask */
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#define PMC_IMR_MCKRDY (0x01 << 3)
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/* PLLA Lock Interrupt Mask */
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#define PMC_IMR_LOCKA (0x01 << 1)
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/* Main Crystal Oscillator Status Interrupt Mask */
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#define PMC_IMR_MOSCXTS (0x01 << 0)
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/* --- PMC Fast Startup Mode Register (PMC_FSMR) --------------------------- */
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/* Low Power Mode */
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#define PMC_FSMR_LPM (0x01 << 20)
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/* USB Alarm Enable */
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#define PMC_FSMR_USBAL (0x01 << 18)
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/* RTC Alarm Enable */
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#define PMC_FSMR_RTCAL (0x01 << 17)
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/* RTC Alarm Enable */
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#define PMC_FSMR_RTTAL (0x01 << 16)
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/* Fast Startup Input Enable 0 to 15 */
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#define PMC_FSMR_FSTT15 (0x01 << 15)
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#define PMC_FSMR_FSTT14 (0x01 << 14)
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#define PMC_FSMR_FSTT13 (0x01 << 13)
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#define PMC_FSMR_FSTT12 (0x01 << 12)
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#define PMC_FSMR_FSTT11 (0x01 << 11)
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#define PMC_FSMR_FSTT10 (0x01 << 10)
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#define PMC_FSMR_FSTT9 (0x01 << 9)
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#define PMC_FSMR_FSTT8 (0x01 << 8)
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#define PMC_FSMR_FSTT7 (0x01 << 7)
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#define PMC_FSMR_FSTT6 (0x01 << 6)
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#define PMC_FSMR_FSTT5 (0x01 << 5)
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#define PMC_FSMR_FSTT4 (0x01 << 4)
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#define PMC_FSMR_FSTT3 (0x01 << 3)
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#define PMC_FSMR_FSTT2 (0x01 << 2)
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#define PMC_FSMR_FSTT1 (0x01 << 1)
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#define PMC_FSMR_FSTT0 (0x01 << 0)
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/* --- PMC Fast Startup Polarity Register (PMC_FSPR) ----------------------- */
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/* Fast Startup Input Polarity x */
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#define PMC_FSPR_FSTP15 (0x01 << 15)
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#define PMC_FSPR_FSTP14 (0x01 << 14)
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#define PMC_FSPR_FSTP13 (0x01 << 13)
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#define PMC_FSPR_FSTP12 (0x01 << 12)
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#define PMC_FSPR_FSTP11 (0x01 << 11)
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#define PMC_FSPR_FSTP10 (0x01 << 10)
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#define PMC_FSPR_FSTP9 (0x01 << 9)
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#define PMC_FSPR_FSTP8 (0x01 << 8)
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#define PMC_FSPR_FSTP7 (0x01 << 7)
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#define PMC_FSPR_FSTP6 (0x01 << 6)
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#define PMC_FSPR_FSTP5 (0x01 << 5)
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#define PMC_FSPR_FSTP4 (0x01 << 4)
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#define PMC_FSPR_FSTP3 (0x01 << 3)
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#define PMC_FSPR_FSTP2 (0x01 << 2)
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#define PMC_FSPR_FSTP1 (0x01 << 1)
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#define PMC_FSPR_FSTP0 (0x01 << 0)
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/* --- PMC Fault Output Clear Register (PMC_FOCR) -------------------------- */
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/* Fault Output Clear */
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#define PMC_FOCR_FOCLR (0x01 << 0)
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/* --- PMC Write Protect Mode Register (PMC_WPMR) -------------------------- */
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/* Write Protect Key */
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#define PMC_WPMR_WPKEY_SHIFT 8
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#define PMC_WPMR_WPKEY (0x504D43 << PMC_WPMR_WPKEY_SHIFT)
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/* Write Protect Enable */
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#define PMC_WPMR_WPEN (0x01 << 0)
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/* --- PMC Write Protect Status Register (PMC_WPSR) ------------------------ */
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/* Write Protect Violation Source */
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#define PMC_WPSR_WPVSRC_SHIFT 8
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#define PMC_WPSR_WPVSRC_MASK (0xFFFF << PMC_WPSR_WPVSRC_SHIFT)
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/* Write Protect Violation Status */
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#define PMC_WPSR_WPVS (0x01 << 0)
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extern uint32_t pmc_mck_frequency;
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enum mck_src {
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MCK_SRC_SLOW = 0,
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MCK_SRC_MAIN = 1,
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MCK_SRC_PLLA = 2,
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MCK_SRC_UPLL = 3,
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};
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void pmc_mck_set_source(enum mck_src src);
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void pmc_xtal_enable(bool en, uint8_t startup_time);
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void pmc_plla_config(uint8_t mul, uint8_t div);
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void pmc_peripheral_clock_enable(uint8_t pid);
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void pmc_peripheral_clock_disable(uint8_t pid);
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void pmc_clock_setup_in_xtal_12mhz_out_84mhz(void);
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void pmc_clock_setup_in_rc_4mhz_out_84mhz(void);
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#endif
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#else
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#warning "pmc_common_all.h should not be included explicitly, only via pmc.h"
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#endif
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