f67e217ffb
The adc v2 periph has the same register map, but comes in two flavours, one supporting injected channels, more watchdogs, per channel sampling times and so on, and one "simple" version. Pull up the f3 and f0 portions into the appropriate files, after comparing with L0 and L4 reference manuals, even if those are not fully landed yet.
157 lines
5.5 KiB
C
157 lines
5.5 KiB
C
/** @addtogroup adc_defines
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@author @htmlonly © @endhtmlonly 2015 Karl Palsson <karlp@tweak.net.au>
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2015 Karl Palsson <karlp@tweak.net.au>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA ADC.H
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The order of header inclusion is important. adc.h includes the device
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specific memorymap.h header before including this header file.*/
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/** @cond */
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#ifdef LIBOPENCM3_ADC_H
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/** @endcond */
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#ifndef LIBOPENCM3_ADC_COMMON_V2_MULTI_H
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#define LIBOPENCM3_ADC_COMMON_V2_MULTI_H
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/*
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* The adc v2 peripheral optionally supports per channel sampling, injected
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* sequences, watchdogs, offsets and other "advanced" features, and is
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* found on the (so far) F3 and L4,
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* or only a much "simpler" version as found on (so far) f0 and l0.
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*/
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/* ----- ADC registers -----------------------------------------------------*/
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/* Sample Time Register 2 */
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#define ADC_SMPR2(adc) MMIO32((adc) + 0x18)
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/* Watchdog Threshold Register 2 */
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#define ADC_TR2(adc) MMIO32((adc) + 0x24)
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/* Watchdog Threshold Register 3 */
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#define ADC_TR3(adc) MMIO32((adc) + 0x28)
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/* Regular Sequence Register x (ADCx_SQRy, x=1..4, y=1..4) SQRy */
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#define ADC_SQR1(adc) MMIO32((adc) + 0x30)
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#define ADC_SQR2(adc) MMIO32((adc) + 0x34)
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#define ADC_SQR3(adc) MMIO32((adc) + 0x38)
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#define ADC_SQR4(adc) MMIO32((adc) + 0x3C)
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/* Injected Sequence Register (ADCx_JSQR, x=1..4) JSQR */
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#define ADC_JSQR(adc) MMIO32((adc) + 0x30)
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/* Offset Register x (ADCx_OFRy, x=1..4) (y=1..4) OFRy */
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#define ADC_OFR1(adc) MMIO32((adc) + 0x60)
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#define ADC_OFR2(adc) MMIO32((adc) + 0x64)
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#define ADC_OFR3(adc) MMIO32((adc) + 0x68)
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#define ADC_OFR4(adc) MMIO32((adc) + 0x6C)
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/* Injected Data Register y (ADCx_JDRy, x=1..4, y= 1..4) JDRy */
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#define ADC_JDR1(adc) MMIO32((adc) + 0x80)
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#define ADC_JDR2(adc) MMIO32((adc) + 0x84)
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#define ADC_JDR3(adc) MMIO32((adc) + 0x88)
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#define ADC_JDR4(adc) MMIO32((adc) + 0x8C)
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/* Analog Watchdog 2 Configuration Register (ADCx_AWD2CR, x=1..4) AWD2CR */
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#define ADC_AWD2CR(adc) MMIO32((adc) + 0xA0)
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/* Analog Watchdog 3 Configuration Register (ADCx_AWD3CR, x=1..4) AWD3CR */
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#define ADC_AWD3CR(adc) MMIO32((adc) + 0xA4)
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/* Differential Mode Selection Register 2 (ADCx_DIFSEL, x=1..4) DIFSEL */
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#define ADC_DIFSEL(adc) MMIO32((adc) + 0xB0)
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/* Calibration Factors (ADCx_CALFACT, x=1..4) CALFACT */
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#define ADC_CALFACT(adc) MMIO32((adc) + 0xB4)
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/* ADC common (shared) registers */
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#define ADC_CSR(adc) MMIO32((adc) + 0x300 + 0x0)
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#define ADC_CDR(adc) MMIO32((adc) + 0x300 + 0xa)
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/* --- Register values ------------------------------------------------------*/
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/* ADC_ISR Values -----------------------------------------------------------*/
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/* QOVF: Injected context queue overflow */
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#define ADC_ISR_JQOVF (1 << 10)
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/* AWD3: Analog watchdog 3 flag */
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#define ADC_ISR_AWD3 (1 << 9)
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/* AWD2: Analog watchdog 2 flag */
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#define ADC_ISR_AWD2 (1 << 8)
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/* JEOS: Injected channel end of sequence flag */
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#define ADC_ISR_JEOS (1 << 6)
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/* JEOC: Injected channel end of conversion flag */
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#define ADC_ISR_JEOC (1 << 5)
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/* ADC_IER Values -----------------------------------------------------------*/
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/* JQOVFIE: Injected context queue overflow interrupt enable */
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#define ADC_IER_JQOVFIE (1 << 10)
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/* AWD3IE: Analog watchdog 3 interrupt enable */
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#define ADC_IER_AWD3IE (1 << 9)
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/* AWD2IE: Analog watchdog 2 interrupt enable */
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#define ADC_IER_AWD2IE (1 << 8)
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/* JEOSIE: End of injected sequence of conversions interrupt enable */
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#define ADC_IER_JEOSIE (1 << 6)
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/* JEOCIE: End of injected conversion interrupt enable */
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#define ADC_IER_JEOCIE (1 << 5)
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/* ADC_CR Values ------------------------------------------------------------*/
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/* ADCALDIF: Differential mode for calibration */
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#define ADC_CR_ADCALDIF (1 << 30)
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/* JADSTP: ADC stop of injected conversion command */
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#define ADC_CR_JADSTP (1 << 5)
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/* JADSTART: ADC start of injected conversion */
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#define ADC_CR_JADSTART (1 << 3)
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/* ADC_CFGR1 Values ---------------------------------------------------------*/
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/* JAUTO: Autoamtic injected group conversion */
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#define ADC_CFGR1_JAUTO (1 << 25)
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/* JAWD1EN: Analog watchdog 1 enable on injected channels */
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#define ADC_CFGR1_JAWD1EN (1 << 24)
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/* JQM: JSQR queue mode */
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#define ADC_CFGR1_JQM (1 << 21)
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/* JDISCEN: Discontinuous mode on injected channels */
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#define ADC_CFGR1_JDISCEN (1 << 20)
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/* DISCNUM[2:0]: Discontinuous mode channel count */
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#define ADC_CFGR1_DISCNUM_SHIFT 17
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#define ADC_CFGR1_DISCNUM_MASK (0x7 << ADC_CFGR1_DISCNUM_SHIFT)
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#define ADC_CFGR1_DISCNUM_VAL(x) (((x) - 1) << ADC_CFGR1_DISCNUM_SHIFT)
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/* EXTSEL[3:0]: External trigger selection for regular group */
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#define ADC_CFGR1_EXTSEL_SHIFT 6
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#define ADC_CFGR1_EXTSEL_MASK (0xf << ADC_CFGR1_EXTSEL_SHIFT)
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#define ADC_CFGR1_EXTSEL_VAL(x) ((x) << ADC_CFGR1_EXTSEL_SHIFT)
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/* --- Function prototypes ------------------------------------------------- */
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BEGIN_DECLS
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END_DECLS
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#endif
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#endif /* LIBOPENCM3_ADC_H */
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/**@}*/
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