7681597e42
When compiling with all warnings enabled, some defines can lead to warning due to missing unsigned type suffix: warning: integer overflow in expression [-Woverflow] This fix should not affected behavior at all, since calculation with such overflows lead to the same actual address when writing to that location. However, it makes the warning disappear and also defines the right data type for a memory location.
88 lines
2.9 KiB
C
88 lines
2.9 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_CM3_MEMORYMAP_H
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#define LIBOPENCM3_CM3_MEMORYMAP_H
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/* --- ARM Cortex-M0, M3 and M4 specific definitions ----------------------- */
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/* Private peripheral bus - Internal */
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#define PPBI_BASE (0xE0000000U)
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/* Those defined only on ARMv7 and above */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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/* ITM: Instrumentation Trace Macrocell */
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#define ITM_BASE (PPBI_BASE + 0x0000)
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/* DWT: Data Watchpoint and Trace unit */
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#define DWT_BASE (PPBI_BASE + 0x1000)
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/* FPB: Flash Patch and Breakpoint unit */
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#define FPB_BASE (PPBI_BASE + 0x2000)
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#endif
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/* PPBI_BASE + 0x3000 (0xE000 3000 - 0xE000 DFFF): Reserved */
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#define SCS_BASE (PPBI_BASE + 0xE000)
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/* PPBI_BASE + 0xF000 (0xE000 F000 - 0xE003 FFFF): Reserved */
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/* Those defined only on ARMv7 and above */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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#define TPIU_BASE (PPBI_BASE + 0x40000)
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#endif
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/* --- SCS: System Control Space --- */
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/* Those defined only on ARMv7 and above */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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/* ITR: Interrupt Type Register */
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#define ITR_BASE (SCS_BASE + 0x0000)
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#endif
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/* SYS_TICK: System Timer */
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#define SYS_TICK_BASE (SCS_BASE + 0x0010)
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/* NVIC: Nested Vector Interrupt Controller */
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#define NVIC_BASE (SCS_BASE + 0x0100)
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/* SCB: System Control Block */
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#define SCB_BASE (SCS_BASE + 0x0D00)
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#ifdef CM0_PLUS
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/* MPU: Memory protection unit */
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#define MPU_BASE (SCS_BASE + 0x0D90)
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#endif
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/* Those defined only on CM0*/
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#if defined(__ARM_ARCH_6M__)
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/* DEBUG: Debug control and configuration */
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#define DEBUG_BASE (SCS_BASE + 0x0DF0)
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#endif
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/* Those defined only on ARMv7 and above */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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/* STE: Software Trigger Interrupt Register */
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#define STIR_BASE (SCS_BASE + 0x0F00)
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/* ID: ID space */
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#define ID_BASE (SCS_BASE + 0x0FD0)
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#endif
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#endif
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