3f0bbf6153
The direct access definitions to the SHPR1 SHPR2 and SHPR3 were simply wrong, and though a handy macro for directly reaching any priority field was provided, the definitions of the fields assumed direct access to the registers. Provide field definitions that match the handy macro, and correct the direct access definitions for people wishing to use them.
445 lines
15 KiB
C
445 lines
15 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_SCB_H
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#define LIBOPENCM3_SCB_H
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#include <libopencm3/cm3/memorymap.h>
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#include <libopencm3/cm3/common.h>
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/* --- SCB: Registers ------------------------------------------------------ */
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/* CPUID: CPUID base register */
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#define SCB_CPUID MMIO32(SCB_BASE + 0x00)
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/* ICSR: Interrupt Control State Register */
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#define SCB_ICSR MMIO32(SCB_BASE + 0x04)
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/* VTOR: Vector Table Offset Register */
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#define SCB_VTOR MMIO32(SCB_BASE + 0x08)
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/* AIRCR: Application Interrupt and Reset Control Register */
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#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C)
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/* SCR: System Control Register */
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#define SCB_SCR MMIO32(SCB_BASE + 0x10)
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/* CCR: Configuration Control Register */
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#define SCB_CCR MMIO32(SCB_BASE + 0x14)
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/* SHP: System Handler Priority Registers */
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/* Note: 12 8bit registers */
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#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id)
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#define SCB_SHPR1 MMIO32(SCB_BASE + 0x18)
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#define SCB_SHPR2 MMIO32(SCB_BASE + 0x1C)
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#define SCB_SHPR3 MMIO32(SCB_BASE + 0x20)
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/* Those defined only on ARMv7 and above */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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/* SHCSR: System Handler Control and State Register */
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#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
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/* CFSR: Configurable Fault Status Registers */
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#define SCB_CFSR MMIO32(SCB_BASE + 0x28)
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/* HFSR: Hard Fault Status Register */
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#define SCB_HFSR MMIO32(SCB_BASE + 0x2C)
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/* DFSR: Debug Fault Status Register */
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#define SCB_DFSR MMIO32(SCB_BASE + 0x30)
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/* MMFAR: Memory Manage Fault Address Register */
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#define SCB_MMFAR MMIO32(SCB_BASE + 0x34)
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/* BFAR: Bus Fault Address Register */
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#define SCB_BFAR MMIO32(SCB_BASE + 0x38)
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/* AFSR: Auxiliary Fault Status Register */
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#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
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/* ID_PFR0: Processor Feature Register 0 */
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#define SCB_ID_PFR0 MMIO32(SCB_BASE + 0x40)
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/* ID_PFR1: Processor Feature Register 1 */
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#define SCB_ID_PFR1 MMIO32(SCB_BASE + 0x44)
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/* ID_DFR0: Debug Features Register 0 */
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#define SCB_ID_DFR0 MMIO32(SCB_BASE + 0x48)
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/* ID_AFR0: Auxiliary Features Register 0 */
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#define SCB_ID_AFR0 MMIO32(SCB_BASE + 0x4C)
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/* ID_MMFR0: Memory Model Feature Register 0 */
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#define SCB_ID_MMFR0 MMIO32(SCB_BASE + 0x50)
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/* ID_MMFR1: Memory Model Feature Register 1 */
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#define SCB_ID_MMFR1 MMIO32(SCB_BASE + 0x54)
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/* ID_MMFR2: Memory Model Feature Register 2 */
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#define SCB_ID_MMFR2 MMIO32(SCB_BASE + 0x58)
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/* ID_MMFR3: Memory Model Feature Register 3 */
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#define SCB_ID_MMFR3 MMIO32(SCB_BASE + 0x5C)
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/* ID_ISAR0: Instruction Set Attributes Register 0 */
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#define SCB_ID_ISAR0 MMIO32(SCB_BASE + 0x60)
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/* ID_ISAR1: Instruction Set Attributes Register 1 */
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#define SCB_ID_ISAR1 MMIO32(SCB_BASE + 0x64)
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/* ID_ISAR2: Instruction Set Attributes Register 2 */
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#define SCB_ID_ISAR2 MMIO32(SCB_BASE + 0x68)
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/* ID_ISAR3: Instruction Set Attributes Register 3 */
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#define SCB_ID_ISAR3 MMIO32(SCB_BASE + 0x6C)
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/* ID_ISAR4: Instruction Set Attributes Register 4 */
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#define SCB_ID_ISAR4 MMIO32(SCB_BASE + 0x70)
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/* CPACR: Coprocessor Access Control Register */
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#define SCB_CPACR MMIO32(SCB_BASE + 0x88)
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/* FPCCR: Floating-Point Context Control Register */
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#define SCB_FPCCR MMIO32(SCB_BASE + 0x234)
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/* FPCAR: Floating-Point Context Address Register */
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#define SCB_FPCAR MMIO32(SCB_BASE + 0x238)
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/* FPDSCR: Floating-Point Default Status Control Register */
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#define SCB_FPDSCR MMIO32(SCB_BASE + 0x23C)
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/* MVFR0: Media and Floating-Point Feature Register 0 */
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#define SCB_MVFR0 MMIO32(SCB_BASE + 0x240)
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/* MVFR1: Media and Floating-Point Feature Register 1 */
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#define SCB_MVFR1 MMIO32(SCB_BASE + 0x244)
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#endif
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/* --- SCB values ---------------------------------------------------------- */
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/* --- SCB_CPUID values ---------------------------------------------------- */
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/* Implementer[31:24]: Implementer code */
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#define SCB_CPUID_IMPLEMENTER_LSB 24
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#define SCB_CPUID_IMPLEMENTER (0xFF << SCB_CPUID_IMPLEMENTER_LSB)
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/* Variant[23:20]: Variant number */
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#define SCB_CPUID_VARIANT_LSB 20
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#define SCB_CPUID_VARIANT (0xF << SCB_CPUID_VARIANT_LSB)
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/* Constant[19:16]: Reads as 0xF (ARMv7-M) M3, M4 */
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/* Constant[19:16]: Reads as 0xC (ARMv6-M) M0, M0+ */
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#define SCB_CPUID_CONSTANT_LSB 16
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#define SCB_CPUID_CONSTANT (0xF << SCB_CPUID_CONSTANT_LSB)
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#define SCB_CPUID_CONSTANT_ARMV6 (0xC << SCB_CPUID_CONSTANT_LSB)
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#define SCB_CPUID_CONSTANT_ARMV7 (0xF << SCB_CPUID_CONSTANT_LSB)
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/* PartNo[15:4]: Part number of the processor */
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#define SCB_CPUID_PARTNO_LSB 4
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#define SCB_CPUID_PARTNO (0xFFF << SCB_CPUID_PARTNO_LSB)
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/* Revision[3:0]: Revision number */
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#define SCB_CPUID_REVISION_LSB 0
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#define SCB_CPUID_REVISION (0xF << SCB_CPUID_REVISION_LSB)
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/* --- SCB_ICSR values ----------------------------------------------------- */
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/* NMIPENDSET: NMI set-pending bit */
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#define SCB_ICSR_NMIPENDSET (1 << 31)
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/* Bits [30:29]: reserved - must be kept cleared */
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/* PENDSVSET: PendSV set-pending bit */
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#define SCB_ICSR_PENDSVSET (1 << 28)
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/* PENDSVCLR: PendSV clear-pending bit */
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#define SCB_ICSR_PENDSVCLR (1 << 27)
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/* PENDSTSET: SysTick exception set-pending bit */
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#define SCB_ICSR_PENDSTSET (1 << 26)
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/* PENDSTCLR: SysTick exception clear-pending bit */
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#define SCB_ICSR_PENDSTCLR (1 << 25)
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/* Bit 24: reserved - must be kept cleared */
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/* Bit 23: reserved for debug - reads as 0 when not in debug mode */
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#define SCB_ICSR_ISRPREEMPT (1 << 23)
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/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */
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#define SCB_ICSR_ISRPENDING (1 << 22)
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/* VECTPENDING[21:12] Pending vector */
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#define SCB_ICSR_VECTPENDING_LSB 12
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#define SCB_ICSR_VECTPENDING (0x1FF << SCB_ICSR_VECTPENDING_LSB)
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/* RETOBASE: Return to base level */
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#define SCB_ICSR_RETOBASE (1 << 11)
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/* Bits [10:9]: reserved - must be kept cleared */
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/* VECTACTIVE[8:0] Active vector */
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#define SCB_ICSR_VECTACTIVE_LSB 0
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#define SCB_ICSR_VECTACTIVE (0x1FF << SCB_ICSR_VECTACTIVE_LSB)
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/* --- SCB_VTOR values ----------------------------------------------------- */
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/* IMPLEMENTATION DEFINED */
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#if defined(__ARM_ARCH_6M__)
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#define SCB_VTOR_TBLOFF_LSB 7
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#define SCB_VTOR_TBLOFF (0x1FFFFFF << SCB_VTOR_TBLOFF_LSB)
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#elif defined(CM1)
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/* VTOR not defined there */
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#elif defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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/* Bits [31:30]: reserved - must be kept cleared */
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/* TBLOFF[29:9]: Vector table base offset field */
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/* inconsistent datasheet - LSB could be 11 */
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/* BUG: TBLOFF is in the ARMv6 Architecture reference manual defined from b7 */
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#define SCB_VTOR_TBLOFF_LSB 9
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#define SCB_VTOR_TBLOFF (0x7FFFFF << SCB_VTOR_TBLOFF_LSB)
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#endif
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/* --- SCB_AIRCR values ---------------------------------------------------- */
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/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */
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#define SCB_AIRCR_VECTKEYSTAT_LSB 16
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#define SCB_AIRCR_VECTKEYSTAT (0xFFFF << SCB_AIRCR_VECTKEYSTAT_LSB)
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#define SCB_AIRCR_VECTKEY (0x05FA << SCB_AIRCR_VECTKEYSTAT_LSB)
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/* ENDIANESS Data endianness bit */
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#define SCB_AIRCR_ENDIANESS (1 << 15)
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/* Those defined only on ARMv7 and above */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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/* Bits [14:11]: reserved - must be kept cleared */
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/* PRIGROUP[10:8]: Interrupt priority grouping field */
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#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8)
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#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8)
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#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 (0x5 << 8)
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#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 (0x6 << 8)
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#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 (0x7 << 8)
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#define SCB_AIRCR_PRIGROUP_MASK (0x7 << 8)
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#define SCB_AIRCR_PRIGROUP_SHIFT 8
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/* Bits [7:3]: reserved - must be kept cleared */
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#endif
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/* SYSRESETREQ System reset request */
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#define SCB_AIRCR_SYSRESETREQ (1 << 2)
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/* VECTCLRACTIVE */
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#define SCB_AIRCR_VECTCLRACTIVE (1 << 1)
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/* Those defined only on ARMv7 and above */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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/* VECTRESET */
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#define SCB_AIRCR_VECTRESET (1 << 0)
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#endif
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/* --- SCB_SCR values ------------------------------------------------------ */
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/* Bits [31:5]: reserved - must be kept cleared */
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/* SEVEONPEND Send Event on Pending bit */
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#define SCB_SCR_SEVEONPEND (1 << 4)
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/* Bit 3: reserved - must be kept cleared */
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/* SLEEPDEEP */
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#define SCB_SCR_SLEEPDEEP (1 << 2)
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/* SLEEPONEXIT */
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#define SCB_SCR_SLEEPONEXIT (1 << 1)
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/* Bit 0: reserved - must be kept cleared */
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/* --- SCB_CCR values ------------------------------------------------------ */
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/* Bits [31:10]: reserved - must be kept cleared */
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/* STKALIGN */
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#define SCB_CCR_STKALIGN (1 << 9)
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/* Those defined only on ARMv7 and above */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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/* BFHFNMIGN */
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#define SCB_CCR_BFHFNMIGN (1 << 8)
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/* Bits [7:5]: reserved - must be kept cleared */
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/* DIV_0_TRP */
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#define SCB_CCR_DIV_0_TRP (1 << 4)
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#endif
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/* UNALIGN_TRP */
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#define SCB_CCR_UNALIGN_TRP (1 << 3)
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/* Those defined only on ARMv7 and above */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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/* Bit 2: reserved - must be kept cleared */
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/* USERSETMPEND */
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#define SCB_CCR_USERSETMPEND (1 << 1)
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/* NONBASETHRDENA */
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#define SCB_CCR_NONBASETHRDENA (1 << 0)
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#endif
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/* These numbers are designed to be used with the SCB_SHPR() macro */
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/* SCB_SHPR1 */
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#define SCB_SHPR_PRI_4_MEMMANAGE 0
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#define SCB_SHPR_PRI_5_BUSFAULT 1
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#define SCB_SHPR_PRI_6_USAGEFAULT 2
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#define SCB_SHPR_PRI_7_RESERVED 3
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/* SCB_SHPR2 */
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#define SCB_SHPR_PRI_8_RESERVED 4
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#define SCB_SHPR_PRI_9_RESERVED 5
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#define SCB_SHPR_PRI_10_RESERVED 6
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#define SCB_SHPR_PRI_11_SVCALL 7
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/* SCB_SHPR3 */
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#define SCB_SHPR_PRI_12_RESERVED 8
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#define SCB_SHPR_PRI_13_RESERVED 9
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#define SCB_SHPR_PRI_14_PENDSV 10
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#define SCB_SHPR_PRI_15_SYSTICK 11
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/* Those defined only on ARMv7 and above */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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/* --- SCB_SHCSR values ---------------------------------------------------- */
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/* Bits [31:19]: reserved - must be kept cleared */
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/* USGFAULTENA: Usage fault enable */
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#define SCB_SHCSR_USGFAULTENA (1 << 18)
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/* BUSFAULTENA: Bus fault enable */
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#define SCB_SHCSR_BUSFAULTENA (1 << 17)
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/* MEMFAULTENA: Memory management fault enable */
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#define SCB_SHCSR_MEMFAULTENA (1 << 16)
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/* SVCALLPENDED: SVC call pending */
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#define SCB_SHCSR_SVCALLPENDED (1 << 15)
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/* BUSFAULTPENDED: Bus fault exception pending */
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#define SCB_SHCSR_BUSFAULTPENDED (1 << 14)
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/* MEMFAULTPENDED: Memory management fault exception pending */
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#define SCB_SHCSR_MEMFAULTPENDED (1 << 13)
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/* USGFAULTPENDED: Usage fault exception pending */
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#define SCB_SHCSR_USGFAULTPENDED (1 << 12)
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/* SYSTICKACT: SysTick exception active */
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#define SCB_SHCSR_SYSTICKACT (1 << 11)
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/* PENDSVACT: PendSV exception active */
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#define SCB_SHCSR_PENDSVACT (1 << 10)
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/* Bit 9: reserved - must be kept cleared */
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/* MONITORACT: Debug monitor active */
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#define SCB_SHCSR_MONITORACT (1 << 8)
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/* SVCALLACT: SVC call active */
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#define SCB_SHCSR_SVCALLACT (1 << 7)
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/* Bits [6:4]: reserved - must be kept cleared */
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/* USGFAULTACT: Usage fault exception active */
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#define SCB_SHCSR_USGFAULTACT (1 << 3)
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/* Bit 2: reserved - must be kept cleared */
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/* BUSFAULTACT: Bus fault exception active */
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#define SCB_SHCSR_BUSFAULTACT (1 << 1)
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/* MEMFAULTACT: Memory management fault exception active */
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#define SCB_SHCSR_MEMFAULTACT (1 << 0)
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/* --- SCB_CFSR values ----------------------------------------------------- */
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/* Bits [31:26]: reserved - must be kept cleared */
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/* DIVBYZERO: Divide by zero usage fault */
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#define SCB_CFSR_DIVBYZERO (1 << 25)
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/* UNALIGNED: Unaligned access usage fault */
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#define SCB_CFSR_UNALIGNED (1 << 24)
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/* Bits [23:20]: reserved - must be kept cleared */
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/* NOCP: No coprocessor usage fault */
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#define SCB_CFSR_NOCP (1 << 19)
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/* INVPC: Invalid PC load usage fault */
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#define SCB_CFSR_INVPC (1 << 18)
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/* INVSTATE: Invalid state usage fault */
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#define SCB_CFSR_INVSTATE (1 << 17)
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/* UNDEFINSTR: Undefined instruction usage fault */
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#define SCB_CFSR_UNDEFINSTR (1 << 16)
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/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */
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#define SCB_CFSR_BFARVALID (1 << 15)
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/* Bits [14:13]: reserved - must be kept cleared */
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/* STKERR: Bus fault on stacking for exception entry */
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#define SCB_CFSR_STKERR (1 << 12)
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/* UNSTKERR: Bus fault on unstacking for a return from exception */
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#define SCB_CFSR_UNSTKERR (1 << 11)
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/* IMPRECISERR: Imprecise data bus error */
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#define SCB_CFSR_IMPRECISERR (1 << 10)
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/* PRECISERR: Precise data bus error */
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#define SCB_CFSR_PRECISERR (1 << 9)
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/* IBUSERR: Instruction bus error */
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#define SCB_CFSR_IBUSERR (1 << 8)
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/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */
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#define SCB_CFSR_MMARVALID (1 << 7)
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/* Bits [6:5]: reserved - must be kept cleared */
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/* MSTKERR: Memory manager fault on stacking for exception entry */
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#define SCB_CFSR_MSTKERR (1 << 4)
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/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */
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#define SCB_CFSR_MUNSTKERR (1 << 3)
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/* Bit 2: reserved - must be kept cleared */
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/* DACCVIOL: Data access violation flag */
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#define SCB_CFSR_DACCVIOL (1 << 1)
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/* IACCVIOL: Instruction access violation flag */
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#define SCB_CFSR_IACCVIOL (1 << 0)
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/* --- SCB_HFSR values ----------------------------------------------------- */
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/* DEBUG_VT: reserved for debug use */
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#define SCB_HFSR_DEBUG_VT (1 << 31)
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/* FORCED: Forced hard fault */
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#define SCB_HFSR_FORCED (1 << 30)
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/* Bits [29:2]: reserved - must be kept cleared */
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/* VECTTBL: Vector table hard fault */
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#define SCB_HFSR_VECTTBL (1 << 1)
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/* Bit 0: reserved - must be kept cleared */
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/* --- SCB_MMFAR values ---------------------------------------------------- */
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/* MMFAR [31:0]: Memory management fault address */
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/* --- SCB_BFAR values ----------------------------------------------------- */
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/* BFAR [31:0]: Bus fault address */
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/* --- SCB_CPACR values ---------------------------------------------------- */
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/* CPACR CPn: Access privileges values */
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#define SCB_CPACR_NONE 0 /* Access denied */
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#define SCB_CPACR_PRIV 1 /* Privileged access only */
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#define SCB_CPACR_FULL 3 /* Full access */
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/* CPACR [20:21]: Access privileges for coprocessor 10 */
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#define SCB_CPACR_CP10 (1 << 20)
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/* CPACR [22:23]: Access privileges for coprocessor 11 */
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#define SCB_CPACR_CP11 (1 << 22)
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#endif
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/* --- SCB functions ------------------------------------------------------- */
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BEGIN_DECLS
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struct scb_exception_stack_frame {
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uint32_t r0;
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uint32_t r1;
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uint32_t r2;
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uint32_t r3;
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uint32_t r12;
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uint32_t lr;
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uint32_t pc;
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uint32_t xpsr;
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} __attribute__((packed));
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#define SCB_GET_EXCEPTION_STACK_FRAME(f) \
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do { \
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asm volatile ("mov %[frameptr], sp" \
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: [frameptr]"=r" (f)); \
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} while (0)
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void scb_reset_system(void) __attribute__((noreturn, naked));
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/* Those defined only on ARMv7 and above */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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void scb_reset_core(void) __attribute__((noreturn, naked));
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void scb_set_priority_grouping(uint32_t prigroup);
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#endif
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END_DECLS
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#endif
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