ec9fc5c122
ITM Stimulus ports need to be accessible with different sizes
The amount of data written out is determined by the size of the write.
Writing a full 32 bit value when you only need 8 for printf() style
substantially reduces the available bandwidth of the SWO
Note: this is an API change for doing 32bit writes.
Old:
ITM_STIM[stimulus_port] = value
New:
ITM_STIM32(stimulus_port) = value
This api is much more in common with some of the other registers that
behave this way. As there's very little (if any) code already using
this API, it's a good time to fix it permanently.
Remove misleading ITM register definitions
ITM_SSPSR is the supported parallel trace size, in _bits_
ITM_CSPSR is in _bits_ as well. There's really no advantage in even
having these sorts of definitions in libopencm3, as these settings are
normally controlled from the debugger side, not the target itself.
Lock and lock status register definitions were added, as per ARM:
"For ARMv7-M, the component ID registers are required for the ROM table,
and the CoreSight management lock access mechanism is defined for the
DWT, ITM, FPB and TPIU blocks."
351 lines
13 KiB
C
351 lines
13 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
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* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_CM3_SCS_H
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#define LIBOPENCM3_CM3_SCS_H
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/*
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* All the definition hereafter are generic for CortexMx ARMv7-M
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* See ARM document "ARMv7-M Architecture Reference Manual" for more details.
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* See also ARM document "ARM Compiler toolchain Developing Software for ARM
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* Processors" for details on System Timer/SysTick.
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*/
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/*
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* The System Control Space (SCS) is a memory-mapped 4KB address space that
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* provides 32-bit registers for configuration, status reporting and control.
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* The SCS registers divide into the following groups:
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* - system control and identification
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* - the CPUID processor identification space
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* - system configuration and status
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* - fault reporting
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* - a system timer, SysTick
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* - a Nested Vectored Interrupt Controller (NVIC)
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* - a Protected Memory System Architecture (PMSA)
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* - system debug.
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*/
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/* System Handler Priority 8 bits Registers, SHPR1/2/3 */
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/* Note: 12 8bit Registers */
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#define SCS_SHPR(ipr_id) MMIO8(SCS_BASE + 0xD18 + ipr_id)
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/*
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* Debug Halting Control and Status Register (DHCSR).
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*
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* Purpose Controls halting debug.
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* Usage constraints: The effect of modifying the C_STEP or C_MASKINTS bit when
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* the system is running with halting debug enabled is UNPREDICTABLE.
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* Halting debug is enabled when C_DEBUGEN is set to 1. The system is running
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* when S_HALT is set to 0.
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* - When C_DEBUGEN is set to 0, the processor ignores the values of all other
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* bits in this register.
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* - For more information about the use of DHCSR see Debug stepping on page
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* C1-824.
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* Configurations Always implemented.
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*/
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/* SCS_DHCSR register */
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#define SCS_DHCSR MMIO32(SCS_BASE + 0xDF0)
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/*
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* Debug Core Register Selector Register (DCRSR).
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*
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* Purpose With the DCRDR, the DCRSR provides debug access to the ARM core
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* registers, special-purpose registers, and Floating-point extension
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* registers. A write to DCRSR specifies the register to transfer, whether the
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* transfer is a read or a write, and starts the transfer.
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* Usage constraints: Only accessible in Debug state.
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* Configurations Always implemented.
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*
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*/
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/* SCS_DCRS register */
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#define SCS_DCRSR MMIO32(SCS_BASE + 0xDF4)
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/*
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* Debug Core Register Data Register (DCRDR)
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*
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* Purpose With the DCRSR, see Debug Core Register Selector Register, the DCRDR
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* provides debug access to the ARM core registers, special-purpose registers,
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* and Floating-point extension registers. The DCRDR is the data register for
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* these accesses.
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* - Used on its own, the DCRDR provides a message passing resource between an
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* external debugger and a debug agent running on the processor.
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* Note:
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* The architecture does not define any handshaking mechanism for this use of
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* DCRDR.
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* Usage constraints: See Use of DCRSR and DCRDR for constraints that apply to
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* particular transfers using the DCRSR and DCRDR.
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* Configurations Always implemented.
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*
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*/
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/* SCS_DCRDR register */
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#define SCS_DCRDR MMIO32(SCS_BASE + 0xDF8)
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/*
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* Debug Exception and Monitor Control Register (DEMCR).
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*
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* Purpose Manages vector catch behavior and DebugMonitor handling when
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* debugging.
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* Usage constraints:
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* - Bits [23:16] provide DebugMonitor exception control.
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* - Bits [15:0] provide Debug state, halting debug, control.
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* Configurations Always implemented.
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*
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*/
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/* SCS_DEMCR register */
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#define SCS_DEMCR MMIO32(SCS_BASE + 0xDFC)
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/* Debug Halting Control and Status Register (DHCSR) */
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#define SCS_DHCSR_DBGKEY 0xA05F0000
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#define SCS_DHCSR_C_DEBUGEN 0x00000001
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#define SCS_DHCSR_C_HALT 0x00000002
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#define SCS_DHCSR_C_STEP 0x00000004
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#define SCS_DHCSR_C_MASKINTS 0x00000008
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#define SCS_DHCSR_C_SNAPSTALL 0x00000020
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#define SCS_DHCSR_S_REGRDY 0x00010000
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#define SCS_DHCSR_S_HALT 0x00020000
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#define SCS_DHCSR_S_SLEEP 0x00040000
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#define SCS_DHCSR_S_LOCKUP 0x00080000
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#define SCS_DHCSR_S_RETIRE_ST 0x01000000
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#define SCS_DHCSR_S_RESET_ST 0x02000000
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/* Debug Core Register Selector Register (DCRSR) */
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#define SCS_DCRSR_REGSEL_MASK 0x0000001F
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#define SCS_DCRSR_REGSEL_XPSR 0x00000010
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#define SCS_DCRSR_REGSEL_MSP 0x00000011
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#define SCS_DCRSR_REGSEL_PSP 0x00000012
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/* Debug Exception and Monitor Control Register (DEMCR) */
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/* Bits 31:25 - Reserved */
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#define SCS_DEMCR_TRCENA (1 << 24)
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/* Bits 23:20 - Reserved */
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#define SCS_DEMCR_MON_REQ (1 << 19)
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#define SCS_DEMCR_MON_STEP (1 << 18)
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#define SCS_DEMCR_VC_MON_PEND (1 << 17)
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#define SCS_DEMCR_VC_MON_EN (1 << 16)
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/* Bits 15:11 - Reserved */
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#define SCS_DEMCR_VC_HARDERR (1 << 10)
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#define SCS_DEMCR_VC_INTERR (1 << 9)
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#define SCS_DEMCR_VC_BUSERR (1 << 8)
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#define SCS_DEMCR_VC_STATERR (1 << 7)
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#define SCS_DEMCR_VC_CHKERR (1 << 6)
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#define SCS_DEMCR_VC_NOCPERR (1 << 5)
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#define SCS_DEMCR_VC_MMERR (1 << 4)
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/* Bits 3:1 - Reserved */
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#define SCS_DEMCR_VC_CORERESET (1 << 0)
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/*
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* System Control Space (SCS) => System timer register support in the SCS.
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* To configure SysTick, load the interval required between SysTick events to
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* the SysTick Reload Value register. The timer interrupt, or COUNTFLAG bit in
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* the SysTick Control and Status register, is activated on the transition from
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* 1 to 0, therefore it activates every n+1 clock ticks. If you require a
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* period of 100, write 99 to the SysTick Reload Value register. The SysTick
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* Reload Value register supports values between 0x1 and 0x00FFFFFF.
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*
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* If you want to use SysTick to generate an event at a timed interval, for
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* example 1ms, you can use the SysTick Calibration Value Register to scale
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* your value for the Reload register. The SysTick Calibration Value Register
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* is a read-only register that contains the number of pulses for a period of
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* 10ms, in the TENMS field, bits[23:0].
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*
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* This register also has a SKEW bit. Bit[30] == 1 indicates that the
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* calibration for 10ms in the TENMS section is not exactly 10ms due to clock
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* frequency. Bit[31] == 1 indicates that the reference clock is not provided.
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*/
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/*
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* SysTick Control and Status Register (CSR).
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* Purpose Controls the system timer and provides status data.
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* Usage constraints: There are no usage constraints.
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* Configurations Always implemented.
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*/
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#define SCS_SYST_CSR MMIO32(SCS_BASE + 0x10)
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/* SysTick Reload Value Register (CVR).
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* Purpose Reads or clears the current counter value.
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* Usage constraints:
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* - Any write to the register clears the register to zero.
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* - The counter does not provide read-modify-write protection.
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* - Unsupported bits are read as zero
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* Configurations Always implemented.
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*/
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#define CM_SCS_SYST_RVR MMIO32(SCS_BASE + 0x14)
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/* SysTick Current Value Register (RVR).
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* Purpose Holds the reload value of the SYST_CVR.
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* Usage constraints There are no usage constraints.
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* Configurations Always implemented.
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*/
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#define CM_SCS_SYST_CVR MMIO32(SCS_BASE + 0x18)
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/*
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* SysTick Calibration value Register(Read Only) (CALIB)
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* Purpose Reads the calibration value and parameters for SysTick.
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* Usage constraints: There are no usage constraints.
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* Configurations Always implemented.
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*/
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#define CM_SCS_SYST_CALIB MMIO32(SCS_BASE + 0x1C)
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/* --- SCS_SYST_CSR values ----------------------------------------------- */
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/* Counter is operating. */
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#define SCS_SYST_CSR_ENABLE (BIT0)
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/* Count to 0 changes the SysTick exception status to pending. */
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#define SCS_SYST_CSR_TICKINT (BIT1)
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/* SysTick uses the processor clock. */
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#define SCS_SYST_CSR_CLKSOURCE (BIT2)
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/*
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* Indicates whether the counter has counted to 0 since the last read of this
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* register:
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* 0 = Timer has not counted to 0
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* 1 = Timer has counted to 0.
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*/
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#define SCS_SYST_CSR_COUNTFLAG (BIT16)
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/* --- CM_SCS_SYST_RVR values ---------------------------------------------- */
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/* Bit 0 to 23 => RELOAD The value to load into the SYST_CVR when the counter
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* reaches 0.
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*/
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/* Bit 24 to 31 are Reserved */
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/* --- CM_SCS_SYST_CVR values ---------------------------------------------- */
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/* Bit0 to 31 => Reads or clears the current counter value. */
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/* --- CM_SCS_SYST_CALIB values -------------------------------------------- */
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/*
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* Bit0 to 23 => TENMS Optionally, holds a reload value to be used for 10ms
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* (100Hz) timing, subject to system clock skew errors. If this field is zero,
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* the calibration value is not known.
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*/
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#define SCS_SYST_SYST_CALIB_TENMS_MASK (BIT24-1)
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/*
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* Bit30 => SKEW Indicates whether the 10ms calibration value is exact:
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* 0 = 10ms calibration value is exact.
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* 1 = 10ms calibration value is inexact, because of the clock frequency
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*/
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#define SCS_SYST_SYST_CALIB_VALUE_INEXACT (BIT30)
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/*
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* Bit31 => NOREF Indicates whether the IMPLEMENTATION DEFINED reference clock
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* is implemented:
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* 0 = The reference clock is implemented.
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* 1 = The reference clock is not implemented.
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* When this bit is 1, the CLKSOURCE bit of the SYST_CSR register is forced to
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* 1 and cannot be cleared to 0.
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*/
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#define SCS_SYST_SYST_CALIB_REF_NOT_IMPLEMENTED (BIT31)
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/*
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* System Control Space (SCS) => Data Watchpoint and Trace (DWT).
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* See "ARMv7-M Architecture Reference Manual"
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* (https://github.com/libopencm3/libopencm3-archive/blob/master/arm/
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* ARMv7-M_ARM.pdf)
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* The DWT is an optional debug unit that provides watchpoints, data tracing,
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* and system profiling for the processor.
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*/
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/*
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* DWT Control register
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* Purpose Provides configuration and status information for the DWT block, and
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* used to control features of the block
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* Usage constraints: There are no usage constraints.
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* Configurations Always implemented.
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*/
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#define SCS_DWT_CTRL MMIO32(DWT_BASE + 0x00)
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/*
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* DWT_CYCCNT register
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* Cycle Count Register (Shows or sets the value of the processor cycle
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* counter, CYCCNT)
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* When enabled, CYCCNT increments on each processor clock cycle. On overflow,
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* CYCCNT wraps to zero.
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*
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* Purpose Shows or sets the value of the processor cycle counter, CYCCNT.
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* Usage constraints: The DWT unit suspends CYCCNT counting when the processor
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* is in Debug state.
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* Configurations Implemented: only when DWT_CTRL.NOCYCCNT is RAZ, see Control
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* register, DWT_CTRL.
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* When DWT_CTRL.NOCYCCNT is RAO no cycle counter is implemented and this
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* register is UNK/SBZP.
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*/
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#define SCS_DWT_CYCCNT MMIO32(DWT_BASE + 0x04)
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/* DWT_CPICNT register
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* Purpose Counts additional cycles required to execute multi-cycle
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* instructions and instruction fetch stalls.
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* Usage constraints: The counter initializes to 0 when software enables its
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* counter overflow event by
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* setting the DWT_CTRL.CPIEVTENA bit to 1.
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* Configurations Implemented: only when DWT_CTRL.NOPRFCNT is RAZ, see Control
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* register, DWT_CTRL.
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* If DWT_CTRL.NOPRFCNT is RAO, indicating that the implementation does not
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* include the profiling counters, this register is UNK/SBZP.
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*/
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#define SCS_DWT_CPICNT MMIO32(DWT_BASE + 0x08)
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/* DWT_EXCCNT register */
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#define SCS_DWT_EXCCNT MMIO32(DWT_BASE + 0x0C)
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/* DWT_EXCCNT register */
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#define SCS_DWT_SLEEPCNT MMIO32(DWT_BASE + 0x10)
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/* DWT_EXCCNT register */
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#define SCS_DWT_LSUCNT MMIO32(DWT_BASE + 0x14)
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/* DWT_EXCCNT register */
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#define SCS_DWT_FOLDCNT MMIO32(DWT_BASE + 0x18)
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/* DWT_PCSR register */
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#define SCS_DWT_PCSR MMIO32(DWT_BASE + 0x18)
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/* CoreSight Lock Status Register for this peripheral */
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#define SCS_DWT_LSR MMIO32(SCS_DWT_BASE + 0xFB4)
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/* CoreSight Lock Access Register for this peripheral */
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#define SCS_DWT_LAR MMIO32(SCS_DWT_BASE + 0xFB0)
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/* --- SCS_DWT_CTRL values ------------------------------------------------- */
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/*
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* Enables CYCCNT:
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* 0 = Disabled, 1 = Enabled
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* This bit is UNK/SBZP if the NOCYCCNT bit is RAO.
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*/
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#define SCS_DWT_CTRL_CYCCNTENA (BIT0)
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/* CoreSight Lock Status Register lock status bit */
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#define SCS_LSR_SLK (1<<1)
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/* CoreSight Lock Status Register lock availability bit */
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#define SCS_LSR_SLI (1<<0)
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/* CoreSight Lock Access key, common for all */
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#define SCS_LAR_KEY 0xC5ACCE55
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/* TODO bit definition values for other DWT_XXX register */
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/* Macro to be called at startup to enable SCS & Cycle Counter */
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#define SCS_DWT_CYCLE_COUNTER_ENABLED() ((SCS_DEMCR |= SCS_DEMCR_TRCENA)\
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(SCS_DWT_CTRL |= SCS_DWT_CTRL_CYCCNTENA))
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#define SCS_SYSTICK_DISABLED() (SCS_SYST_CSR = 0)
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/* Macro to be called at startup to Enable CortexMx SysTick (but IRQ not
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* enabled)
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*/
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#define SCS_SYSTICK_ENABLED() (SCS_SYST_CSR = (SCS_SYST_CSR_ENABLE | \
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SCS_SYST_CSR_CLKSOURCE))
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/* Macro to be called at startup to Enable CortexMx SysTick and IRQ */
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#define SCS_SYSTICK_AND_IRQ_ENABLED() (SCS_SYST_CSR = (SCS_SYST_CSR_ENABLE | \
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SCS_SYST_CSR_CLKSOURCE | \
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SCS_SYST_CSR_TICKINT))
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#endif
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