7816501dbc
to remove variations, redundancies, add missing, fix errors. All c files refer only to the dispatch style headers in /include/stm32. Those headers #include memorymap.h and cm3/common.h. All references to these are removed from the family specific headers. Ethernet untouched as it appears incomplete. Added dummy spi.c for F0/F3. Fix some doxygen anomalies.
132 lines
4.8 KiB
C
132 lines
4.8 KiB
C
/** @defgroup CRS_defines CRS Defines
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*
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* @brief <b>Defined Constants and Types for the STM32F0xx Clock Recovery</b>
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*
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* @ingroup STM32F0xx_defines
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*
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* @version 1.0.0
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*
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* @date 5 Feb 2014
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2014 Frantisek Burian <BuFran@seznam.cz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_CRS_H
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#define LIBOPENCM3_CRS_H
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/**@{*/
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/*****************************************************************************/
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/* Module definitions */
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/*****************************************************************************/
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#define CRS CRS_BASE
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/*****************************************************************************/
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/* Register definitions */
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/*****************************************************************************/
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#define CRS_CR MMIO32(CRS_BASE + 0x00)
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#define CRS_CFGR MMIO32(CRS_BASE + 0x04)
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#define CRS_ISR MMIO32(CRS_BASE + 0x08)
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#define CRS_ICR MMIO32(CRS_BASE + 0x0c)
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/*****************************************************************************/
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/* Register values */
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/*****************************************************************************/
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/* CEC_CR Values ------------------------------------------------------------*/
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#define CRS_CR_TRIM_SHIFT 8
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#define CRS_CR_TRIM (0x3F << CRS_CR_TRIM_SHIFT)
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#define CRS_CR_SWSYNC (1 << 7)
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#define CRS_CR_AUTOTRIMEN (1 << 6)
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#define CRS_CR_CEN (1 << 5)
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#define CRS_CR_ESYNCIE (1 << 3)
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#define CRS_CR_ERRIE (1 << 2)
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#define CRS_CR_SYNCWARNIE (1 << 1)
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#define CRS_CR_SYNCOKIE (1 << 0)
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/* CEC_CFGR Values ----------------------------------------------------------*/
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#define CRS_CFGR_SYNCPOL (1 << 31)
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#define CRS_CFGR_SYNCSRC_SHIFT 28
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#define CRS_CFGR_SYNCSRC (3 << CRS_CFGR_SYNCSRC_SHIFT)
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#define CRS_CFGR_SYNCSRC_GPIO (0 << CRS_CFGR_SYNCSRC_SHIFT)
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#define CRS_CFGR_SYNCSRC_LSE (1 << CRS_CFGR_SYNCSRC_SHIFT)
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#define CRS_CFGR_SYNCSRC_USB_SOF (2 << CRS_CFGR_SYNCSRC_SHIFT)
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#define CRS_CFGR_SYNCDIV_SHIFT 24
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#define CRS_CFGR_SYNCDIV (7 << CRS_CFGR_SYNCDIV_SHIFT)
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#define CRS_CFGR_SYNCDIV_NODIV (0 << CRS_CFGR_SYNCDIV_SHIFT)
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#define CRS_CFGR_SYNCDIV_DIV2 (1 << CRS_CFGR_SYNCDIV_SHIFT)
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#define CRS_CFGR_SYNCDIV_DIV4 (2 << CRS_CFGR_SYNCDIV_SHIFT)
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#define CRS_CFGR_SYNCDIV_DIV8 (3 << CRS_CFGR_SYNCDIV_SHIFT)
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#define CRS_CFGR_SYNCDIV_DIV16 (4 << CRS_CFGR_SYNCDIV_SHIFT)
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#define CRS_CFGR_SYNCDIV_DIV32 (5 << CRS_CFGR_SYNCDIV_SHIFT)
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#define CRS_CFGR_SYNCDIV_DIV64 (6 << CRS_CFGR_SYNCDIV_SHIFT)
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#define CRS_CFGR_SYNCDIV_DIV128 (7 << CRS_CFGR_SYNCDIV_SHIFT)
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#define CRS_CFGR_FELIM_SHIFT 16
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#define CRS_CFGR_FELIM (0xFF << CRS_CFGR_FELIM_SHIFT)
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#define CRS_CFGR_FELIM_VAL(x) ((x) << CRS_CFGR_FELIM_SHIFT)
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#define CRS_CFGR_RELOAD_SHIFT 0
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#define CRS_CFGR_RELOAD (0xFFFF << CRS_CFGR_RELOAD_SHIFT)
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#define CRS_CFGR_RELOAD_VAL(x) ((x) << CRS_CFGR_RELOAD_SHIFT)
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/* CEC_ISR Values -----------------------------------------------------------*/
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#define CRS_ISR_FECAP_SHIFT 16
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#define CRS_ISR_FECAP (0xFFFF << CRS_ISR_FECAP_SHIFT)
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#define CRS_ISR_FEDIR (1 << 15)
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#define CRS_ISR_TRIMOVF (1 << 10)
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#define CRS_ISR_SYNCMISS (1 << 9)
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#define CRS_ISR_SYNCERR (1 << 8)
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#define CRS_ISR_ESYNCF (1 << 3)
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#define CRS_ISR_ERRF (1 << 2)
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#define CRS_ISR_SYNCWARNF (1 << 1)
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#define CRS_ISR_SYNCOOKF (1 << 0)
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/* CEC_ICR Values -----------------------------------------------------------*/
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#define CRS_ICR_ESYNCC (1 << 3)
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#define CRS_ICR_ERRC (1 << 2)
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#define CRS_ICR_SYNCWARNC (1 << 1)
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#define CRS_ICR_SYNCOKC (1 << 0)
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/*****************************************************************************/
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/* API definitions */
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/*****************************************************************************/
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/*****************************************************************************/
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/* API Functions */
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/*****************************************************************************/
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BEGIN_DECLS
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END_DECLS
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/**@}*/
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#endif
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