94 lines
3.6 KiB
C
94 lines
3.6 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_MEMORYMAP_H
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#define LIBOPENCM3_MEMORYMAP_H
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#include <libopencm3/cm3/memorymap.h>
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/* --- STM32 specific peripheral definitions ------------------------------- */
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/* Memory map for all busses */
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#define PERIPH_BASE (0x40000000U)
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#define IOPORT_BASE (0x50000000U)
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#define INFO_BASE (0x1ff80000U)
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#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)
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#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)
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#define PERIPH_BASE_AHB (PERIPH_BASE + 0x20000)
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/* Register boundary addresses */
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/* APB1 */
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#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)
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#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)
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#define LCD_BASE (PERIPH_BASE_APB1 + 0x2400)
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#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800)
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#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)
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#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)
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#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)
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#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
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#define LPUART1_BASE (PERIPH_BASE_APB1 + 0x4800)
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#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)
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#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)
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#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00)
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#define USB_SRAM_BASE (PERIPH_BASE_APB1 + 0x6000)
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#define CRS_BASE (PERIPH_BASE_APB1 + 0x6C00)
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#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)
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#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400)
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#define LPTIM1_BASE (PERIPH_BASE_APB1 + 0x7c00)
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/* APB2 */
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#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000)
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#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)
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#define TIM21_BASE (PERIPH_BASE_APB2 + 0x0800)
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#define TIM22_BASE (PERIPH_BASE_APB2 + 0x1400)
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#define FIREWALL_BASE (PERIPH_BASE_APB2 + 0x1C00)
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#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2400)
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#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)
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#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800)
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#define DBGMCU_BASE (PERIPH_BASE_APB2 + 0x5800)
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/* AHB */
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#define DMA1_BASE (PERIPH_BASE_AHB + 0x00000)
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#define RCC_BASE (PERIPH_BASE_AHB + 0x01000)
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#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x02000)
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#define CRC_BASE (PERIPH_BASE_AHB + 0x03000)
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#define TSC_BASE (PERIPH_BASE_AHB + 0x04000)
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#define RNG_BASE (PERIPH_BASE_AHB + 0x05000)
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#define AES_BASE (PERIPH_BASE_AHB + 0x06000)
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#define GPIO_PORT_A_BASE (IOPORT_BASE + 0x00000)
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#define GPIO_PORT_B_BASE (IOPORT_BASE + 0x00400)
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#define GPIO_PORT_C_BASE (IOPORT_BASE + 0x00800)
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#define GPIO_PORT_D_BASE (IOPORT_BASE + 0x00c00)
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#define GPIO_PORT_H_BASE (IOPORT_BASE + 0x01C00)
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/* Device Electronic Signature */
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#define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x7C)
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#define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x50)
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#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)
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#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)
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#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 0x14)
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/* ST provided factory calibration values @ 3.0V */
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#define ST_VREFINT_CAL MMIO16((INFO_BASE + 0x78))
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#define ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0x7A))
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#define ST_TSENSE_CAL2_110C MMIO16((INFO_BASE + 0x7E))
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#endif
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