c557ef96f9
Was attempting to run add to the f4 docs, which aren't referenced from the f7 doxygen build, obviously.
195 lines
6.2 KiB
C
195 lines
6.2 KiB
C
/** @defgroup adc_defines ADC Defines
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@brief <b>Defined Constants and Types for the STM32F7xx Analog to Digital
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Converters</b>
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@ingroup STM32F7xx_defines
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2019
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Matthew Lai <m@matthewlai.ca>
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@author @htmlonly © @endhtmlonly 2009
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Edward Cheeseman <evbuilder@users.sourceforge.net>
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@date 31 August 2012
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2019 Matthew Lai <m@matthewlai.ca>
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* Copyright (C) 2009 Edward Cheeseman <evbuilder@users.sourceforge.net>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_ADC_H
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#define LIBOPENCM3_ADC_H
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#include <libopencm3/stm32/common/adc_common_v1_multi.h>
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/* ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) */
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#define ADC_JOFR1(block) MMIO32((block) + 0x14)
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#define ADC_JOFR2(block) MMIO32((block) + 0x18)
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#define ADC_JOFR3(block) MMIO32((block) + 0x1c)
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#define ADC_JOFR4(block) MMIO32((block) + 0x20)
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/* ADC watchdog high threshold register (ADC_HTR) */
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#define ADC_HTR(block) MMIO32((block) + 0x24)
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/* ADC watchdog low threshold register (ADC_LTR) */
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#define ADC_LTR(block) MMIO32((block) + 0x28)
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/* ADC regular sequence register 1 (ADC_SQR1) */
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#define ADC_SQR1(block) MMIO32((block) + 0x2c)
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/* ADC regular sequence register 2 (ADC_SQR2) */
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#define ADC_SQR2(block) MMIO32((block) + 0x30)
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/* ADC regular sequence register 3 (ADC_SQR3) */
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#define ADC_SQR3(block) MMIO32((block) + 0x34)
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/* ADC injected sequence register (ADC_JSQR) */
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#define ADC_JSQR(block) MMIO32((block) + 0x38)
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/* ADC injected data register x (ADC_JDRx) (x=1..4) */
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#define ADC_JDR1(block) MMIO32((block) + 0x3c)
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#define ADC_JDR2(block) MMIO32((block) + 0x40)
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#define ADC_JDR3(block) MMIO32((block) + 0x44)
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#define ADC_JDR4(block) MMIO32((block) + 0x48)
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/* ADC regular data register (ADC_DR) */
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#define ADC_DR(block) MMIO32((block) + 0x4c)
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/** @defgroup adc_channel ADC Channel Numbers
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* @ingroup adc_defines
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*@{*/
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#define ADC_CHANNEL_TEMP 18
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#define ADC_CHANNEL_VREF 17
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#define ADC_CHANNEL_VBAT 18
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/**@}*/
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/* --- ADC_CR1 values (note some of these are defined elsewhere) ----------- */
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#define ADC_CR1_AWDCH_MAX 18
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/* --- Convenience macros -------------------------------------------------- */
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/* EXTSEL[3:0]: External event selection for regular group. */
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/****************************************************************************/
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/** @defgroup adc_trigger_regular ADC Trigger Identifier for Regular group
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@ingroup adc_defines
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@{*/
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/** Timer 1 Compare Output 1 */
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#define ADC_CR2_EXTSEL_TIM1_CC1 (0x0 << 24)
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/** Timer 1 Compare Output 2 */
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#define ADC_CR2_EXTSEL_TIM1_CC2 (0x1 << 24)
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/** Timer 1 Compare Output 3 */
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#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 24)
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/** Timer 2 Compare Output 2 */
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#define ADC_CR2_EXTSEL_TIM2_CC2 (0x3 << 24)
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/** Timer 5 TRGO Event */
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#define ADC_CR2_EXTSEL_TIM5_TRGO (0x4 << 24)
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/** Timer 4 Compare Output 4 */
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#define ADC_CR2_EXTSEL_TIM4_CC4 (0x5 << 24)
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/** Timer 3 Compare Output 4 */
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#define ADC_CR2_EXTSEL_TIM3_CC4 (0x6 << 24)
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/** Timer 8 TRGO Event */
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#define ADC_CR2_EXTSEL_TIM8_TRGO (0x7 << 24)
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/** Timer 8 TRGO2 Event */
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#define ADC_CR2_EXTSEL_TIM8_TRGO2 (0x8 << 24)
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/** Timer 1 TRGO Event */
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#define ADC_CR2_EXTSEL_TIM1_TRGO (0x9 << 24)
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/** Timer 1 TRGO2 Event */
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#define ADC_CR2_EXTSEL_TIM1_TRGO2 (0xA << 24)
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/** Timer 2 TRGO Event */
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#define ADC_CR2_EXTSEL_TIM2_TRGO (0xB << 24)
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/** Timer 4 TRGO Event */
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#define ADC_CR2_EXTSEL_TIM4_TRGO (0xC << 24)
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/** Timer 6 TRGO Event */
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#define ADC_CR2_EXTSEL_TIM6_TRGO (0xD << 24)
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/** EXTI Line 11 Event */
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#define ADC_CR2_EXTSEL_EXTI_LINE_11 (0xF << 24)
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/**@}*/
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/* JEXTSEL[3:0]: External event selection for injected group. */
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/****************************************************************************/
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/** @defgroup adc_trigger_injected ADC Trigger Identifier for Injected group
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@ingroup adc_defines
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@{*/
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#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x0 << 16)
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#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x1 << 16)
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#define ADC_CR2_JEXTSEL_TIM2_TRGO (0x2 << 16)
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#define ADC_CR2_JEXTSEL_TIM2_CC1 (0x3 << 16)
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#define ADC_CR2_JEXTSEL_TIM3_CC4 (0x4 << 16)
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#define ADC_CR2_JEXTSEL_TIM4_TRGO (0x5 << 16)
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/* 0x6 undefined */
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#define ADC_CR2_JEXTSEL_TIM8_CC4 (0x7 << 16)
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#define ADC_CR2_JEXTSEL_TIM1_TRGO2 (0x8 << 16)
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#define ADC_CR2_JEXTSEL_TIM8_TRGO (0x9 << 16)
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#define ADC_CR2_JEXTSEL_TIM8_TRGO2 (0xA << 16)
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#define ADC_CR2_JEXTSEL_TIM3_cc3 (0xB << 16)
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#define ADC_CR2_JEXTSEL_TIM5_TRGO (0xC << 16)
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#define ADC_CR2_JEXTSEL_TIM3_CC1 (0xD << 16)
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#define ADC_CR2_JEXTSEL_TIM6_TRGO (0xE << 16)
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/* 0xf undefined */
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/**@}*/
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/* ADC_SMPRG ADC Sample Time Selection for Channels */
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/** @defgroup adc_sample_rg ADC Sample Time Selection for All Channels
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@ingroup adc_defines
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@{*/
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#define ADC_SMPR_SMP_3CYC 0x0
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#define ADC_SMPR_SMP_15CYC 0x1
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#define ADC_SMPR_SMP_28CYC 0x2
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#define ADC_SMPR_SMP_56CYC 0x3
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#define ADC_SMPR_SMP_84CYC 0x4
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#define ADC_SMPR_SMP_112CYC 0x5
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#define ADC_SMPR_SMP_144CYC 0x6
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#define ADC_SMPR_SMP_480CYC 0x7
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/**@}*/
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/* --- ADC_SQR1 values ----------------------------------------------------- */
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#define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB)
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#define ADC_SQR_MAX_CHANNELS_REGULAR 16
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/* ADCPRE: ADC prescaler. */
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/****************************************************************************/
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/** @defgroup adc_ccr_adcpre ADC Prescale
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@ingroup adc_defines
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@{*/
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#define ADC_CCR_ADCPRE_BY2 (0x0 << 16)
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#define ADC_CCR_ADCPRE_BY4 (0x1 << 16)
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#define ADC_CCR_ADCPRE_BY6 (0x2 << 16)
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#define ADC_CCR_ADCPRE_BY8 (0x3 << 16)
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/**@}*/
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#define ADC_CCR_ADCPRE_MASK (0x3 << 16)
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#define ADC_CCR_ADCPRE_SHIFT 16
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BEGIN_DECLS
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void adc_set_multi_mode(uint32_t mode);
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void adc_enable_vbat_sensor(void);
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void adc_disable_vbat_sensor(void);
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END_DECLS
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#endif
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