71 lines
1.8 KiB
C
71 lines
1.8 KiB
C
/** @defgroup lptimer_defines LPTIM Defines
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*
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* @ingroup STM32G0xx_defines
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*
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* @brief <b>libopencm3 Defined Constants and Types for the STM32G0xx Low Power Timer</b>
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*
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* @version 1.0.0
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*
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* LGPL License Terms @ref lgpl_license
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* */
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2019 Guillaume Revaillot <g.revaillot@gmail.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_LPTIMER_H
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#define LIBOPENCM3_LPTIMER_H
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/**@{*/
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#include <libopencm3/stm32/common/lptimer_common_all.h>
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/** @defgroup lptim_reg_base Low Power Timer register base addresses
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@{*/
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#define LPTIM1 LPTIM1_BASE
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#define LPTIM2 LPTIM2_BASE
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/**@}*/
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/** LPTIM_CFGR2 LPTIM configuration register 2 */
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#define LPTIM_CFGR2(tim_base) MMIO32((tim_base) + 0x24)
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/** @addtogroup lptim_cr
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@{*/
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/** COUNTRST Counter reset **/
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#define LPTIM_CR_COUNTRST (1 << 3)
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/** RSTARE Reset after read enable **/
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#define LPTIM_CR_RSTARE (1 << 4)
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/**@}*/
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/** @defgroup lptim_cfgr2 LPTIM_CFGR2 Configuration Register 2
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@{*/
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#define LPTIM_CFGR2_IN2SEL_SHIFT 4
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#define LPTIM_CFGR2_IN2SEL_MASK 0x03
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#define LPTIM_CFGR2_IN1SEL_SHIFT 0
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#define LPTIM_CFGR2_IN1SEL_MASK 0x03
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/**@}*/
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BEGIN_DECLS
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END_DECLS
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/**@}*/
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#endif
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