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Updated PWMDAC test bench

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This commit is contained in:
Niels Moseley 2017-10-10 00:54:20 +02:00
parent 8e3de97977
commit 1d624a482a
3 changed files with 19 additions and 2 deletions
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3
verilog/pwmdac/pwmdac.v
View File

@ -5,6 +5,9 @@
// Niels Moseley - Moseley Instruments 2017
// http://www.moseleyinstruments.com
//
//
// For a 10 kHz output rate, the clock rate should be 2.560 MHz
//
module PWMDAC (
clk,

16
verilog/pwmdac/pwmdac_tb.v
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@ -10,6 +10,8 @@ module PWMDAC_TB;
reg signed [0:7] din;
wire dacout, din_ack;
real accu;
PWMDAC u_pwmdac (
.clk (clk),
.rst_an (rst_an),
@ -25,12 +27,24 @@ module PWMDAC_TB;
clk = 0;
rst_an = 0;
din = 0;
accu = 0;
#3
rst_an = 1;
#10240
#655360
$finish;
end
always @(posedge clk)
begin
if (din_ack)
begin
accu = accu + 1.0/256.0;
if (accu > 1.0)
accu = -1.0;
din = $rtoi($sin(2.0*3.1415927*accu)*127.0);
end
end
always
#5 clk = !clk;

2
verilog/pwmdac/run_tb.bat
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@ -1,5 +1,5 @@
mkdir bin
C:\iverilog\bin\iverilog -o bin\pwmdac.vvp -g2005 -s PWMDAC_TB pwmdac.v pwmdac_tb.v
C:\iverilog\bin\iverilog -o bin\pwmdac.vvp -m va_math -g2005 -s PWMDAC_TB pwmdac.v pwmdac_tb.v
cd bin
C:\iverilog\bin\vvp pwmdac.vvp
cd ..