Fixed python script to generate sign-magnitude coeffs instead of 2s complement ones. Filter engine FSM needs revisiting.

verilog/controller/genctrlrom.py

@@ -44,15 +44,16 @@ def emitRomByte(b):
     RomAddress = RomAddress + 1;
 
 def convertFilterCoeff(c):
-    # turn c into negative 8-bit number
+    # convert 2s complement into
-    # 1 -> 255
+    # sign-magnitude...
-    # 2 -> 254
-    # 255 -> 1
-    # 254 -> 2
-    # 128 -> xxx
-    # 0   -> 0
 
-    return c;
+    smag = c & 0x7F;
+    if (c>=0x80):            # convert unsigned to signed
+        c = (c-0x80) ^ 0x7F;
+        smag = c & 0x7F;    # get magnitude
+        smag = smag | 0x80; # add sign bit
+
+    return smag;
 
 fout = open('ctrlrom.v','wt')
 

verilog/controller/xlat.v

@@ -24,7 +24,7 @@ module XLAT (
     output reg [9:0] c10_out;
     wire sign;
 
-    assign sign = ~c8_in[7];
+    assign sign = c8_in[7];
 
     always@(*)
     begin

verilog/filter/filter.v

@@ -6,6 +6,12 @@
 // http://www.moseleyinstruments.com
 //
 
+//
+// MEH!, the FSM needs a rewrite
+// 
+// * split into clocked and unclocked ALWAYS
+//   and proper state names.
+//
 
 module FILTER (
         clk, 
@@ -21,6 +27,7 @@ module FILTER (
         start,          // trigger processing of the input signal
         done            // goes to '1' when sig_out has valid data
     );
+    parameter DEBUG = 0; //defult value
 
 	//////////// CLOCK //////////
 	input clk;
@@ -117,13 +124,15 @@ module FILTER (
             // update the filter states if necessary
             if (update_states == 1)
             begin
+                state1[0] <= accu;
+                state2[0] <= state1[5];   
+
                 for(i=1; i<6; i=i+1)
                 begin
                     state1[i] <= state1[i-1];
                     state2[i] <= state2[i-1];
                 end
-                state1[0] <= accu;
+                //$display("BOOM %d %d %d %d %d %d %d", accu, state1[0], state1[1], state1[2],state1[3],state1[4],state1[5]);
-                state2[0] <= state1[5];
             end
 
             // update the coefficients if necessary
@@ -177,6 +186,15 @@ module FILTER (
                             state_sel <= 0; // state 1 as mul input
                             mul_start <= 1; // trigger multiplier
                             cur_state <= 4'b0001;
+
+                            if (DEBUG == 1)
+                            begin
+                                for(i=0; i<6; i=i+1)
+                                begin
+                                    $display("Section %d:   %d   %d", i, state1[i], state2[i]);
+                                end
+                            end
+                            
                         end
                     end
                 4'b0001: // Dummy cycle to wait for mul_done
@@ -227,7 +245,9 @@ module FILTER (
 
                         // check if this is the last section..
                         if (section==4'b0110)
+                        begin
                             cur_state <= 4'b0000;   // one complete filter set done..
+                        end
                         else
                             cur_state <= 4'b1000;   // next..
                     end

verilog/filter/filter_tb.v

@@ -13,6 +13,8 @@ module FILTER_TB;
     wire signed [15:0] sig_out;
     wire done;
 
+    defparam u_filter.DEBUG = 1;
+
     FILTER u_filter (
         .clk        (clk),
         .rst_an     (rst_an),
@@ -33,7 +35,7 @@ module FILTER_TB;
         clk    = 0;
         rst_an = 0;
 
-        sig_in      = 16'h0100;
+        sig_in      = 16'h0010;
         coef_in     = 0;
         coef_load   = 0;
         start       = 0;
@@ -46,38 +48,38 @@ module FILTER_TB;
         #10
         coef_load = 1;
         // section 1
-        coef_in     = {1'b0, 9'd64}; // sign-magnitude a1 = -0.25
+        coef_in     = 10'h3C9;
         #10
-        coef_in     = {1'b1, 9'd256}; // sign-magnitude a2 = 0.5
+        coef_in     = 10'h1E4;
         #10
         // section 2
-        coef_in     = {1'b0, 9'd0}; // sign-magnitude a1 = 0;
+        coef_in     = 10'h2B8;
         #10
-        coef_in     = {1'b0, 9'd0}; // sign-magnitude a1 = 0;
+        coef_in     = 10'h1CF;
         #10
         // section 3
-        coef_in     = {1'b0, 9'd0}; // sign-magnitude a1 = 0;
+        coef_in     = 10'h238;
         #10
-        coef_in     = {1'b0, 9'd0}; // sign-magnitude a1 = 0;
+        coef_in     = 10'h080;
         #10
         // section 4
-        coef_in     = {1'b0, 9'd0}; // sign-magnitude a1 = 0;
+        coef_in     = 10'h195;
         #10
-        coef_in     = {1'b0, 9'd0}; // sign-magnitude a1 = 0;
+        coef_in     = 10'h1BF;
         #10
         // section 5
-        coef_in     = {1'b0, 9'd0}; // sign-magnitude a1 = 0;
+        coef_in     = 10'h135;
         #10
-        coef_in     = {1'b0, 9'd0}; // sign-magnitude a1 = 0;
+        coef_in     = 10'h1BF;
         #10
         // section 6
-        coef_in     = {1'b0, 9'd0}; // sign-magnitude a1 = 0;
+        coef_in     = 10'h000;
         #10
-        coef_in     = {1'b0, 9'd0}; // sign-magnitude a1 = 0;
+        coef_in     = 10'h000;
         #10
         coef_load = 0;
         start = 1;
-        #50000;
+        #10000;
         check_finish = 1;
     end
 

verilog/speech256_top/speech256_top_tb.v

@@ -33,7 +33,7 @@ module SPEECH256_TOP_TB;
         #5
         rst_an = 1;
         #5
-        data_in = 6;
+        data_in = 7;
         data_stb = 1;
         #5
         data_stb = 0;