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update DE0 readme.md

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Niels Moseley 2017-10-26 17:07:37 +02:00
parent 1194eec79d
commit 8afd1af0a7
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15
boards/Digilent DE0/README.md
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@ -1,3 +1,18 @@
## Digilent DE0 board
* Altera EP3C16F484C6 FPGA
The DAC output is the UART_TX pin. It _really_ needs a 5kHz lowpass filter, otherwise you'll be deafened/greeted by a very loud 10kHz PWM carrier. Try a 330 ohm series resistor, followed by a 100nF capacitor to ground:
```
UART_TX pin ----RRRRR---------o OUTPUT
|
C
C
C
|
GND
```

5
verilog/speech256_top/speech256_top.v
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@ -72,6 +72,9 @@ module SPEECH256_TOP (
.done (src_strobe)
);
// Note: the sigma-delta DAC sounds bad because it needs
// an interpolator/lowpass filter at the input.
//
`ifdef USE_SDDAC
SD2DAC u_sd2dac (
.clk (clk),
@ -84,7 +87,7 @@ module SPEECH256_TOP (
PWMDAC u_pwmdac (
.clk (clk),
.rst_an (rst_an),
.din (sig_filter[11:4]), // add +24dB gain .. FIXME: add saturation ??
.din (sig_filter[12:5]), // add +18dB gain .. FIXME: add saturation ??
.din_ack (pwmdac_ack),
.dacout (pwm_out)
);