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https://github.com/trcwm/Speech256.git
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Fix bugs in the filter engine FSM. Verified correct behaviour with a 2nd order section.
This commit is contained in:
Niels Moseley
parent
541fb228ed
commit
cf89706963
@ -44,8 +44,8 @@ module FILTER (
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//////////// internal signals //////////
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reg signed [9:0] coefmem [0:11]; // coefficient memory / shift register
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reg signed [15:0] state1 [0:11]; // state 1 memory / shift register
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reg signed [15:0] state2 [0:11]; // state 2 memory / shift register
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reg signed [15:0] state1 [0:5]; // state 1 memory / shift register
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reg signed [15:0] state2 [0:5]; // state 2 memory / shift register
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reg signed [15:0] accu; // accumulator
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reg mul_start;
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@ -55,6 +55,7 @@ module FILTER (
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reg update_states;
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reg update_coeffs;
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reg [3:0] cur_state;
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reg unsigned [2:0] section;
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wire mul_done;
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wire signed [15:0] mul_result, accu_in, mul_in;
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@ -74,8 +75,8 @@ module FILTER (
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);
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// signal input mux for multipliers
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assign mul_in = (state_sel) ? state1[11] : state2[11];
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assign accu_in = (accu_sel) ? sig_in : accu;
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assign mul_in = (state_sel) ? state2[5] : state1[5];
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assign accu_in = (accu_sel) ? accu : sig_in;
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assign mul_coeff = coefmem[11];
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assign sig_out = accu;
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@ -86,10 +87,13 @@ module FILTER (
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// !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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// reset cycle here ..
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// !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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for(i=0; i<12; i=i+1)
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for(i=0; i<6; i=i+1)
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begin
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state1[i] <= 0;
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state2[i] <= 0;
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end
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for(i=0; i<12; i=i+1)
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begin
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coefmem[i] <= 0;
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end
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@ -104,6 +108,7 @@ module FILTER (
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mul_start <= 0;
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cur_state <= 4'b0000;
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done <= 0;
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section <= 0;
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end
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else
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begin
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@ -114,13 +119,13 @@ module FILTER (
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// update the filter states if necessary
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if (update_states == 1)
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begin
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for(i=1; i<12; i=i+1)
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for(i=1; i<6; i=i+1)
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begin
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state1[i] <= state1[i-1];
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state2[i] <= state2[i-1];
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end
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state1[0] <= accu;
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state2[0] <= state1[11];
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state2[0] <= state1[5];
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end
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// update the coefficients if necessary
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@ -135,7 +140,7 @@ module FILTER (
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if (coef_load == 1)
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begin
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coefmem[0] <= coef_in;
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$display("Loaded coefficient: coefmem[0] = %x", coef_in);
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//$display("Loaded coefficient: coefmem[0] = %xh", coef_in);
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end
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else
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coefmem[0] <= coefmem[11];
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@ -158,14 +163,15 @@ module FILTER (
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state_sel <= 0;
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accu_sel <= 0;
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update_states <= 0;
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update_coeffs <= 0;
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update_coeffs <= 0;
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case(cur_state)
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4'b0000: // IDLE state
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begin
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done <= 1;
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section <= 0;
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if (start == 1)
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begin
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// // state1 * coeff[0]
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// state1 * coeff[0]
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state_sel <= 0; // state 1 as mul input
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mul_start <= 1; // trigger multiplier
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cur_state <= 4'b0001;
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@ -175,18 +181,23 @@ module FILTER (
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// to reach a valid state
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begin
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cur_state <= 4'b0010;
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//for(i=0; i<6; i=i+1)
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//begin
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// $display("s1[%d] = %x", i, state1[i]);
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// $display("s2[%d] = %x", i, state2[i]);
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//end
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end
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4'b0010: // wait for multiplier to complete
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begin
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if (mul_done == 1)
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begin
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cur_state <= 4'b0011;
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accu_sel <= 0; // accu = sig_in + mul_result
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do_accu <= 1;
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end
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end
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4'b0011: // update accu
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begin
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accu_sel <= 0; // accu = sig_in + mul_result
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do_accu <= 1;
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4'b0011: // update accu, 1st section only!
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begin
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cur_state <= 4'b0100;
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update_coeffs <= 1; // advance to coeff[1]
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end
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@ -205,20 +216,48 @@ module FILTER (
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begin
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if (mul_done == 1)
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begin
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section <= section + 4'b001; // increment section number
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cur_state <= 4'b0111;
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accu_sel <= 1; // accu = accu + mul_result
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do_accu <= 1;
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end
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end
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4'b0111: // update accumulator and filter states
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begin
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accu_sel <= 1; // accu = accu + mul_result
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do_accu <= 1;
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update_coeffs <= 1; // advance to next section..
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update_states <= 1;
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cur_state <= 4'b0000;
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// check if this is the last section..
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if (section==4'b0110)
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cur_state <= 4'b0000; // one complete filter set done..
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else
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cur_state <= 4'b1000; // next..
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end
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4'b1000: // stop, for now ..
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4'b1000:
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begin
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done <= 1;
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// next section: state1 * coeff[0]
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cur_state <= 4'b1001;
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state_sel <= 0; // state 1 as mul input
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mul_start <= 1; // trigger multiplier
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end
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4'b1001: // Dummy cycle to wait for mul_done
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// to reach a valid state
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begin
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cur_state <= 4'b1010;
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end
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4'b1010: // wait for multiplier to complete
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begin
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if (mul_done == 1)
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begin
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cur_state <= 4'b1011;
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accu_sel <= 1; // accu = accu + mul_result
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do_accu <= 1;
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end
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end
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4'b1011: // update accu, 2nd..5th section only!
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begin
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update_coeffs <= 1; // advance to coeff[1]
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cur_state <= 4'b0100;
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end
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default:
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cur_state <= 4'b0000;
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@ -34,32 +34,59 @@ module FILTER_TB;
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rst_an = 0;
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sig_in = 16'h0100;
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coef_in = 10'h000; // sign-magnitude
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coef_in = 0;
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coef_load = 0;
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start = 0;
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check_finish = 0;
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#10
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rst_an = 1;
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#10
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coef_load = 1;
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coef_in = 10'h21F; // sign-magnitude
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// load all the coefficients
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for(i=1; i<12; i=i+1)
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begin
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#10
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coef_load = 1;
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coef_in = 10'h00F; // sign-magnitude
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end
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#10
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coef_load = 1;
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// section 1
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coef_in = {1'b0, 9'd128}; // sign-magnitude a1 = -0.25
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#10
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coef_in = {1'b1, 9'd256}; // sign-magnitude a2 = 0.5
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#10
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// section 2
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coef_in = {1'b0, 9'd0}; // sign-magnitude a1 = 0;
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#10
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coef_in = {1'b0, 9'd0}; // sign-magnitude a1 = 0;
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#10
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// section 3
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coef_in = {1'b0, 9'd0}; // sign-magnitude a1 = 0;
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#10
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coef_in = {1'b0, 9'd0}; // sign-magnitude a1 = 0;
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#10
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// section 4
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coef_in = {1'b0, 9'd0}; // sign-magnitude a1 = 0;
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#10
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coef_in = {1'b0, 9'd0}; // sign-magnitude a1 = 0;
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#10
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// section 5
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coef_in = {1'b0, 9'd0}; // sign-magnitude a1 = 0;
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#10
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coef_in = {1'b0, 9'd0}; // sign-magnitude a1 = 0;
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#10
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// section 6
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coef_in = {1'b0, 9'd0}; // sign-magnitude a1 = 0;
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#10
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coef_in = {1'b0, 9'd0}; // sign-magnitude a1 = 0;
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#10
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coef_load = 0;
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#10
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start = 1;
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#50000;
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check_finish = 1;
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end
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always@(posedge clk)
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begin
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if ((done == 1) && (coef_load != 1))
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$display("%d", sig_out);
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end
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always
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#5 clk = !clk;
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34
verilog/filter/results.md
Normal file
34
verilog/filter/results.md
Normal file
@ -0,0 +1,34 @@
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# Results
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The testbench should approximately give the following step response results:
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(leading zeroes are okay)
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- 256
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- 320
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- 208
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- 148
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- 189
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- 229
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- 219
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- 196
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- 196
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- 207
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- 210
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- 205
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- 202
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- 204
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- 206
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- 205
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- 204
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- 204
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- 205
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- 205
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- 205
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- 205
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- 205
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- 205
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- 205
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- 205
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- 205
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Note that there might be a few +/- 1 round-off errors.
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@ -141,10 +141,11 @@ module SPMUL (
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begin
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domul <= 0;
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done <= 1;
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// correct for the coeff sign bit
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if (coefreg[9] == 0)
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result_out <= {1'b0, accumulator[23:9]};
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else
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result_out <= {1'b1, ~accumulator[23:9]};
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result_out <= {1'b1, ~accumulator[23:9]} + 1;
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state <= 0;
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end
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default:
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