mirror of
https://github.com/trcwm/Speech256.git
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53 lines
1.8 KiB
Markdown
53 lines
1.8 KiB
Markdown
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An FPGA implementation of a classic 80ies speech synthesizer in Verilog.
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## Introduction
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* Platform agnostic implementation.
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## FPGA requirements
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* 4 K ROM
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Quartus II 13.1 synthesis results (Digilent DE0 board):
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```
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Flow Status Successful - Thu Oct 26 16:47:44 2017
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Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
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Revision Name Speech256_DE0
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Top-level Entity Name Speech256_DE0
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Family Cyclone III
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Device EP3C16F484C6
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Timing Models Final
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Total logic elements 657 / 15,408 ( 4 % )
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Total combinational functions 571 / 15,408 ( 4 % )
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Dedicated logic registers 484 / 15,408 ( 3 % )
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Total registers 484
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Total pins 21 / 347 ( 6 % )
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Total virtual pins 0
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Total memory bits 32,868 / 516,096 ( 6 % )
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Embedded Multiplier 9-bit elements 0 / 112 ( 0 % )
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Total PLLs 0 / 4 ( 0 % )
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```
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## Description of blocks
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### SPMUL
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A serial/parallel multiplier with one 10-bit sign-magnitude and one 2's complement 16-bit input. The 10-bit input range represents -1 .. 1.
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### SOURCE
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The source consists of a LFSR noise generator and a pulse generator with a settable period/duration.
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### FILTER
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A 12-pole filter engine that takes 12 10-bit sign-magnitude filter coefficients and a 16-bit input. The 12-pole filter is built from second-order sections, each having coefficients A1 and A2. Each filter coefficient has a range of -1 .. 1.
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The second-order filter transfer function is H(z) = 1 / (1 - 2 * A1 * z^-1 - A2 * z^-2).
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### CONTROLLER
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The controller reads the allophones from the control bus and generates the necessary signals to drive the source and filter blocks. The parameters for the source and filter are encoded in a 4K ROM by means of high-level instructions.
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## License
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TBD.
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This project was done during the [Retro Challenge 2017/10 contest](http://www.retrochallenge.org).
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<br>
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